Cu wire bonding for fine pitch 65nm silicon integrated circuits

Results of a development program aimed at introducing Cu wire to a low K circuit under pad integrated circuit made in 65nm technology are summarized. The results demonstrate that if the wire bond process is optimized along with the tool design, then it is possible to produce both substrate (PBGA) an...

Full description

Saved in:
Bibliographic Details
Main Authors: Qwai Low, Osenbach, John, YongSeok Yang, KyeongSool Seong, SeokHo Na
Format: Conference Proceeding
Language:English
Subjects:
Bonding
Design optimization
Dielectric devices
Dielectric substrates
Integrated circuit technology
Lead
Robustness
Silicon
Temperature
Wire
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Results of a development program aimed at introducing Cu wire to a low K circuit under pad integrated circuit made in 65nm technology are summarized. The results demonstrate that if the wire bond process is optimized along with the tool design, then it is possible to produce both substrate (PBGA) and lead frame (TQFP) devices with pure Cu wire that show no evidence of damage to the underlining dielectric stack, robust ball bonds and stitch bonds with no evidence of lifts or cracks. Furthermore, the data demonstrate that the fundamental reliability of both packages as determined by temperature cycling, high temperature humidity storage and high temperature storage is more than sufficient if the correct mold compound is used.
ISSN:0569-5503
2377-5726
DOI:10.1109/ECTC.2010.5490847