A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop

This work presents a high timing resolution and wide measured timing range time-to-digital converter (TDC) for all digital phase-locked loop (ADPLL). The multi-phase outputs of digital controlled oscillator (DCO) utilize to sample the timing difference and extend its detectable timing range. A time...

Full description

Saved in:
Bibliographic Details
Main Authors: Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, Hong-Yi Huang
Format: Conference Proceeding
Language:eng ; jpn
Subjects:
all digital PLL (ADPLL)
Clocks
Delay lines
Digital control
digital controlled oscillator (DCO)
Digital-controlled oscillators
multi-phase
Phase frequency detector
Phase locked loops
Pulse amplifiers
Signal resolution
Space vector pulse width modulation
time-to-digital (TDC)
Timing
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This work presents a high timing resolution and wide measured timing range time-to-digital converter (TDC) for all digital phase-locked loop (ADPLL). The multi-phase outputs of digital controlled oscillator (DCO) utilize to sample the timing difference and extend its detectable timing range. A time amplifier (TA) is further applied to enhance the timing resolution. This design requires less silicon area compared to traditional TDCs. The TDC is realized by using a 90 nm CMOS process. TDC achieves a 6.8 ps timing resolution and a measured timing range from 12 ps to 9.5 ns. The DNL and INL are ±0.85 LSB and ±3.5 LSB, respectively. The power dissipation is 240 uW at 0.5 V supply voltage.
DOI:10.1109/DDECS.2010.5491766