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A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop
This work presents a high timing resolution and wide measured timing range time-to-digital converter (TDC) for all digital phase-locked loop (ADPLL). The multi-phase outputs of digital controlled oscillator (DCO) utilize to sample the timing difference and extend its detectable timing range. A time...
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creator | Kuo-Hsing Cheng Chang-Chien Hu Jen-Chieh Liu Hong-Yi Huang |
description | This work presents a high timing resolution and wide measured timing range time-to-digital converter (TDC) for all digital phase-locked loop (ADPLL). The multi-phase outputs of digital controlled oscillator (DCO) utilize to sample the timing difference and extend its detectable timing range. A time amplifier (TA) is further applied to enhance the timing resolution. This design requires less silicon area compared to traditional TDCs. The TDC is realized by using a 90 nm CMOS process. TDC achieves a 6.8 ps timing resolution and a measured timing range from 12 ps to 9.5 ns. The DNL and INL are ±0.85 LSB and ±3.5 LSB, respectively. The power dissipation is 240 uW at 0.5 V supply voltage. |
doi_str_mv | 10.1109/DDECS.2010.5491766 |
format | conference_proceeding |
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The multi-phase outputs of digital controlled oscillator (DCO) utilize to sample the timing difference and extend its detectable timing range. A time amplifier (TA) is further applied to enhance the timing resolution. This design requires less silicon area compared to traditional TDCs. The TDC is realized by using a 90 nm CMOS process. TDC achieves a 6.8 ps timing resolution and a measured timing range from 12 ps to 9.5 ns. The DNL and INL are ±0.85 LSB and ±3.5 LSB, respectively. The power dissipation is 240 uW at 0.5 V supply voltage.</description><identifier>ISBN: 9781424466122</identifier><identifier>ISBN: 1424466121</identifier><identifier>EISBN: 9781424466115</identifier><identifier>EISBN: 9781424466139</identifier><identifier>EISBN: 142446613X</identifier><identifier>EISBN: 1424466113</identifier><identifier>DOI: 10.1109/DDECS.2010.5491766</identifier><language>eng ; jpn</language><publisher>IEEE</publisher><subject>all digital PLL (ADPLL) ; Clocks ; Delay lines ; Digital control ; digital controlled oscillator (DCO) ; Digital-controlled oscillators ; multi-phase ; Phase frequency detector ; Phase locked loops ; Pulse amplifiers ; Signal resolution ; Space vector pulse width modulation ; time-to-digital (TDC) ; Timing</subject><ispartof>13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010, p.285-288</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5491766$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,27904,54898</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5491766$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kuo-Hsing Cheng</creatorcontrib><creatorcontrib>Chang-Chien Hu</creatorcontrib><creatorcontrib>Jen-Chieh Liu</creatorcontrib><creatorcontrib>Hong-Yi Huang</creatorcontrib><title>A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop</title><title>13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems</title><addtitle>DDECS</addtitle><description>This work presents a high timing resolution and wide measured timing range time-to-digital converter (TDC) for all digital phase-locked loop (ADPLL). The multi-phase outputs of digital controlled oscillator (DCO) utilize to sample the timing difference and extend its detectable timing range. A time amplifier (TA) is further applied to enhance the timing resolution. This design requires less silicon area compared to traditional TDCs. The TDC is realized by using a 90 nm CMOS process. TDC achieves a 6.8 ps timing resolution and a measured timing range from 12 ps to 9.5 ns. The DNL and INL are ±0.85 LSB and ±3.5 LSB, respectively. The power dissipation is 240 uW at 0.5 V supply voltage.</description><subject>all digital PLL (ADPLL)</subject><subject>Clocks</subject><subject>Delay lines</subject><subject>Digital control</subject><subject>digital controlled oscillator (DCO)</subject><subject>Digital-controlled oscillators</subject><subject>multi-phase</subject><subject>Phase frequency detector</subject><subject>Phase locked loops</subject><subject>Pulse amplifiers</subject><subject>Signal resolution</subject><subject>Space vector pulse width modulation</subject><subject>time-to-digital (TDC)</subject><subject>Timing</subject><isbn>9781424466122</isbn><isbn>1424466121</isbn><isbn>9781424466115</isbn><isbn>9781424466139</isbn><isbn>142446613X</isbn><isbn>1424466113</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNpVUM1OwzAYC0JIoNEXgEteICNJ89fj1A2GNIkDcJ6-NskIS5uq7ZB4e8o2Dvhi2bJ9MEJ3jM4Zo8XDcrkqX-ecTlqKgmmlLlBWaMMEF0IpxuTlP835NcqG4ZNOEJJTZW7QfoHH0DgyJmLDLowQcZ3aL9ePrseHIbQ73BziGEj3AYMjAzRd_DWhtcciPho-TGmfegwx4r-dUyOmeu8sjil1t-jKQxxcduYZen9cvZVrsnl5ei4XGxKYVCOR2hougfscdMEosByEql3lqGZGK29z4z04aeoKVMEFtaaQlnvFK0YrleczdH_aDc65bdeHBvrv7fmi_AflJVsw</recordid><startdate>201004</startdate><enddate>201004</enddate><creator>Kuo-Hsing Cheng</creator><creator>Chang-Chien Hu</creator><creator>Jen-Chieh Liu</creator><creator>Hong-Yi Huang</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201004</creationdate><title>A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop</title><author>Kuo-Hsing Cheng ; Chang-Chien Hu ; Jen-Chieh Liu ; Hong-Yi Huang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i156t-57d825a2f3a7910a13a46cebe071876fd38ffae58cba69240d895d2f62b10b633</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng ; jpn</language><creationdate>2010</creationdate><topic>all digital PLL (ADPLL)</topic><topic>Clocks</topic><topic>Delay lines</topic><topic>Digital control</topic><topic>digital controlled oscillator (DCO)</topic><topic>Digital-controlled oscillators</topic><topic>multi-phase</topic><topic>Phase frequency detector</topic><topic>Phase locked loops</topic><topic>Pulse amplifiers</topic><topic>Signal resolution</topic><topic>Space vector pulse width modulation</topic><topic>time-to-digital (TDC)</topic><topic>Timing</topic><toplevel>online_resources</toplevel><creatorcontrib>Kuo-Hsing Cheng</creatorcontrib><creatorcontrib>Chang-Chien Hu</creatorcontrib><creatorcontrib>Jen-Chieh Liu</creatorcontrib><creatorcontrib>Hong-Yi Huang</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kuo-Hsing Cheng</au><au>Chang-Chien Hu</au><au>Jen-Chieh Liu</au><au>Hong-Yi Huang</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop</atitle><btitle>13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems</btitle><stitle>DDECS</stitle><date>2010-04</date><risdate>2010</risdate><spage>285</spage><epage>288</epage><pages>285-288</pages><isbn>9781424466122</isbn><isbn>1424466121</isbn><eisbn>9781424466115</eisbn><eisbn>9781424466139</eisbn><eisbn>142446613X</eisbn><eisbn>1424466113</eisbn><abstract>This work presents a high timing resolution and wide measured timing range time-to-digital converter (TDC) for all digital phase-locked loop (ADPLL). The multi-phase outputs of digital controlled oscillator (DCO) utilize to sample the timing difference and extend its detectable timing range. A time amplifier (TA) is further applied to enhance the timing resolution. This design requires less silicon area compared to traditional TDCs. The TDC is realized by using a 90 nm CMOS process. TDC achieves a 6.8 ps timing resolution and a measured timing range from 12 ps to 9.5 ns. The DNL and INL are ±0.85 LSB and ±3.5 LSB, respectively. The power dissipation is 240 uW at 0.5 V supply voltage.</abstract><pub>IEEE</pub><doi>10.1109/DDECS.2010.5491766</doi><tpages>4</tpages></addata></record> |
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identifier | ISBN: 9781424466122 |
ispartof | 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010, p.285-288 |
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language | eng ; jpn |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | all digital PLL (ADPLL) Clocks Delay lines Digital control digital controlled oscillator (DCO) Digital-controlled oscillators multi-phase Phase frequency detector Phase locked loops Pulse amplifiers Signal resolution Space vector pulse width modulation time-to-digital (TDC) Timing |
title | A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop |
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