An efficient hybrid LUT/SOP reconfigurable architecture

With the increasing NRE cost of advanced process technologies, reconfigurable devices receive great attention in small and medium volume IC designs. However, lower logic utilization and slower timing performance limit the efficacy of FPGA and CPLD. In this paper, we propose an efficient hybrid LUT/S...

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Bibliographic Details
Main Authors: Po-Yang Hsu, Ping-Chuan Lu, Yi-Yu Liu
Format: Conference Proceeding
Language:English
Subjects:
Circuit synthesis
Costs
Field programmable gate arrays
Logic design
Logic devices
Performance evaluation
Reconfigurable architectures
Reconfigurable logic
Table lookup
Timing
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Summary:With the increasing NRE cost of advanced process technologies, reconfigurable devices receive great attention in small and medium volume IC designs. However, lower logic utilization and slower timing performance limit the efficacy of FPGA and CPLD. In this paper, we propose an efficient hybrid LUT/SOP reconfigurable design style to exploit both the advantages of LUT-cell and SOP-cell for circuit design. After that, architectural evaluations are performed in order to have the best cell mixture ratio. Furthermore, three logic optimization techniques, cell collapsing, phase flipping, and phase duplication, are proposed for hybrid LUT/SOP FPGA synthesis from a pure LUT-based design. The experimental results demonstrate that our proposed hybrid LUT/SOP design style achieves 35% circuit performance improvement and 51% transistor count reduction as compared with the depth optimal 4-LUT-based FPGA.
DOI:10.1109/VDAT.2010.5496718