Tetragonal \hbox/\hbox\hbox Stack as High- \kappa Gate Dielectric for Si-Based MOS Devices

• Published in: IEEE electron device letters 2010-09, Vol.31 (9), p.1014-1016
• Main Authors: Wu, Yung-Hsien, Chen, Lun-Lun, Lyu, Rong-Jhe, Li, Ming-Yen, Wu, Hsiao-Che
• Format: Article
• Language: English
• Subjects: Amorphous materials; Capacitance; Dielectric devices; Frequency; Grain boundaries; hbox{Al}_{2}\hbox{O}_{3}; high- kappa gate dielectric; Hysteresis; Leakage current; MOS devices; nitridation; passivation; Plasmas; Robustness; tetragonal hbox{ZrO}_{2}
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2010.2053191

Abstract-The combination of tetragonal ZrO 2 (t-ZrO 2 ) and amorphous Al 2 O 3 was explored as the gate dielectric for Si-based MOS devices. Because of the absence of a ZrSiO 4 and/or ZrSi interfacial layer, the thermally stable t-ZrO 2 /Al 2 O 3 /Si stack is more eligible than the Al 2 O 3 /t-ZrO 2 /Si stack for the gate dielectric since it demonstrates larger capacitance, smaller hysteresis, better frequency dispersion, lower leakage current, and more robust reliability. By employing additional NH 3 plasma nitridation to well passivate the grain boundaries of the t-ZrO 2 film, without compromising its κ-value, a greatly reduced leakage current of 2.9 × 10 -8 A/cm 2 can be achieved at gate bias of flatband voltage (V fb )-1 V with an effective oxide thickness of 1.64 nm, which paves a new way to develop a high-performance crystalline gate dielectric for advanced MOS devices.