A generic system simulator (GENESYS) for ASIC technology and architecture beyond 2001

GENESYS, a hierarchical tool for exploring future ASIC technology and architecture, is described and employed to project high-performance ASIC power drain and clock frequency, a roadmap for interconnect design, and performance, energy, and area limits.

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Bibliographic Details
Main Authors: Eble, J.C., De, V.K., Wills, D.S., Meindl, J.D.
Format: Conference Proceeding
Language:English
Subjects:
Application specific integrated circuits
Clocks
Computer architecture
Delay
Frequency
Integrated circuit interconnections
Microelectronics
Packaging
Power system modeling
Space technology
Online Access:Request full text
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Description
Summary:GENESYS, a hierarchical tool for exploring future ASIC technology and architecture, is described and employed to project high-performance ASIC power drain and clock frequency, a roadmap for interconnect design, and performance, energy, and area limits.
ISSN:1063-0988
2164-1773
DOI:10.1109/ASIC.1996.551992