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A Novel Five-Photomask Low-Temperature Polycrystalline Silicon CMOS Structure for AMLCD Application

A novel five-mask low-temperature polycrystalline silicon (LTPS) CMOS structure was verified by manufacturing the thin-film transistor test samples using the proposed five-mask LTPS CMOS process. In integrating the five-mask CMOS structure, a selective contact barrier metal formation process was dev...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2010-09, Vol.57 (9), p.2324-2329
Main Authors: LEE, Sang-Jin, LEE, Seok-Woo, OH, Kum-Mi, PARK, Soo-Jeong, LEE, Kyung-Eon, YOO, Yong-Su, LIM, Kyoung-Moon, YANG, Myoung-Su, YANG, Yong-Suk, HWANG, Yong-Kee
Format: Article
Language:English
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Summary:A novel five-mask low-temperature polycrystalline silicon (LTPS) CMOS structure was verified by manufacturing the thin-film transistor test samples using the proposed five-mask LTPS CMOS process. In integrating the five-mask CMOS structure, a selective contact barrier metal formation process was developed, without additional photomask steps, to solve the issue of high-contact-resistance problem encountered inevitably in the contact between the indium tin oxide and doped polycrystalline silicon (poly-Si) source-drain layers. The five-mask CMOS technology was also confirmed by manufacturing a five-mask CMOS panel for the active-matrix liquid-crystal-display application.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2010.2053868