Error-resilient low-power Viterbi decoders

Two low-power Viterbi decoder (VD) architectures are presented in this paper. In the first, limited decision errors are introduced in the add-compare-select units (ACSUs) of a VD to reduce their critical path delays so that they can be operated at lower supply voltages in absence of timing errors. I...

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Bibliographic Details
Main Authors: Abdallah, Rami A., Shanbhag, Naresh R.
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
algorithmic noise tolerance
Bit error rate
Decoding
Delay
Energy consumption
Error correction
error resilient
Hardware > Robustness
low power
Power system reliability
process variations
Timing
viterbi
Viterbi algorithm
Voltage
voltage overscaling
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Summary:Two low-power Viterbi decoder (VD) architectures are presented in this paper. In the first, limited decision errors are introduced in the add-compare-select units (ACSUs) of a VD to reduce their critical path delays so that they can be operated at lower supply voltages in absence of timing errors. In the second one, we allow data-dependent timing errors which occur whenever a critical path in the ACSU is excited. Algorithmic noise-tolerance (ANT) is then applied at the level of the ACSU to correct for these errors. Power reduction in this design is achieved by either overscaling the supply voltage (voltage overscaling (VOS)) or designing at the nominal process corner and supply voltage (average-case design). Power savings in the first and second design are 58% and 40% at a coding loss of 0:15 dB and 1:1 dB respectively in a IBM 130nm CMOS process.
DOI:10.1145/1393921.1393951