ESD protection design with lateral DMOS transistor in 40-V BCD technology

ESD protection designs for smart power applications with lateral double-diffused MOS (LDMOS) transistor were proposed. With the proposed ESD detection circuits, the n-channel LDMOS can be quickly turned on to protect the output drivers during ESD stress. The proposed ESD protection circuits have bee...

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Bibliographic Details
Main Authors: Chang-Tzu Wang, Ming-Dou Ker, Tien-Hao Tang, Kuan-Cheng Su
Format: Conference Proceeding
Language:English
Subjects:
Breakdown voltage
Clamps
CMOS process
Diodes
Driver circuits
Electrostatic discharge
MOSFETs
Pins
Protection
Stress
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Summary:ESD protection designs for smart power applications with lateral double-diffused MOS (LDMOS) transistor were proposed. With the proposed ESD detection circuits, the n-channel LDMOS can be quickly turned on to protect the output drivers during ESD stress. The proposed ESD protection circuits have been successfully verified in a 0.35-μm 5-V/40-V bipolar CMOS DMOS (BCD) process. In addition, the power-rail ESD protection design can be also achieved with stacked structure to protect 40-V power pins without latchup issue in the smart power ICs.
ISSN:1946-1542
1946-1550
DOI:10.1109/IPFA.2010.5532308