Asynchronous FPGA architecture with distributed control

Asynchronous techniques have become more significant with continued scaling of VLSI technologies. This paper proposes an asynchronous FPGA architecture. Different from previous methods of introducing asynchrony into FPGAs, our method seeks to preserve the current FPGA cell structure as much as possi...

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Bibliographic Details
Main Authors: Delong Shang, Fei Xia, Yakovlev, A
Format: Conference Proceeding
Language:English
Subjects:
Clocks
CMOS logic circuits
CMOS technology
Delay
Distributed control
Energy consumption
Field programmable gate arrays
Integrated circuit interconnections
Nanoscale devices
Wires
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Summary:Asynchronous techniques have become more significant with continued scaling of VLSI technologies. This paper proposes an asynchronous FPGA architecture. Different from previous methods of introducing asynchrony into FPGAs, our method seeks to preserve the current FPGA cell structure as much as possible, whilst achieving delay insensitivity in the inter-cell interconnects. By using David Cells as the central technique in the delay insensitive clock replacement, this method is conducive to the establishment of an automatic design and synthesis flow. It also particularly caters for low power designs, where current FPGA solutions are not effective yet.
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2010.5537316