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Robustness of logic gates and reconfigurability of neuromorphic switching networks

Nanoparticle networks with functional molecular links that show current-voltage characteristics (IVC) with negative differential resistance (NDR) can be trained to perform XOR-AND logic gates (Husband et al. [1]; Skoldberg and Wendin [2]). In this work we investigate the robustness of the Nanocell n...

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Main Authors: Chiragwandi, Z, Sköldberg, J, Wendin, G
Format: Conference Proceeding
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Sköldberg, J
Wendin, G
description Nanoparticle networks with functional molecular links that show current-voltage characteristics (IVC) with negative differential resistance (NDR) can be trained to perform XOR-AND logic gates (Husband et al. [1]; Skoldberg and Wendin [2]). In this work we investigate the robustness of the Nanocell network by removing links until desired logic gates no longer can be configured or operated within our simulation of the network. We present results for the robustness of XOR-AND configured (halfadder) Nanocells, as well as the effects of varying the IVC and NDR characteristics of the linker molecules.
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fullrecord <record><control><sourceid>swepub_6IE</sourceid><recordid>TN_cdi_ieee_primary_5537493</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5537493</ieee_id><sourcerecordid>oai_research_chalmers_se_b840c413_47ed_4862_ab2c_eedf9cd71109</sourcerecordid><originalsourceid>FETCH-LOGICAL-i251t-f3c6ab98961208175e03199f4498e0dde7ea83f1d00bca5f1e0b3fcdba23b9f13</originalsourceid><addsrcrecordid>eNo9kctuwjAQRd0HUinlB9pNfiDUz8ReItQHElIlaNeW7YyDW0iQHYT4-wZBO5vRnXt1FncQeiR4QghWz_PVbLqaUNxrIVjJFbtCY1VKwinngmFFr9GQEiFzIqi4Qfd_hlS3aIhpSXLOMB2gocR5wYveuUPjlL5xP1zQgpVDtFy2dp-6BlLKWp9t2jq4rDYdpMw0VRbBtY0P9T4aGzahO55CDexju23jbt1n0yF0bh2auj93hzb-pAc08GaTYHzZI_T1-vI5e88XH2_z2XSRBypIl3vmCmOVVAWhWJJSAGZEKc-5koCrCkowknlSYWydEZ4Atsy7yhrKrPKEjdDqzE0H2O2t3sWwNfGoWxN0hAQmurV2a7PZQkw6gbaSY8cJ07yESnNZUG0sdRqg8spV5an1nvp0pgYA-GdeHsB-AX3FdZ4</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Robustness of logic gates and reconfigurability of neuromorphic switching networks</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Chiragwandi, Z ; Sköldberg, J ; Wendin, G</creator><creatorcontrib>Chiragwandi, Z ; Sköldberg, J ; Wendin, G</creatorcontrib><description>Nanoparticle networks with functional molecular links that show current-voltage characteristics (IVC) with negative differential resistance (NDR) can be trained to perform XOR-AND logic gates (Husband et al. [1]; Skoldberg and Wendin [2]). In this work we investigate the robustness of the Nanocell network by removing links until desired logic gates no longer can be configured or operated within our simulation of the network. We present results for the robustness of XOR-AND configured (halfadder) Nanocells, as well as the effects of varying the IVC and NDR characteristics of the linker molecules.</description><identifier>ISSN: 0271-4302</identifier><identifier>ISBN: 1424453089</identifier><identifier>ISBN: 9781424453085</identifier><identifier>ISBN: 9781424453092</identifier><identifier>ISBN: 1424453097</identifier><identifier>EISSN: 2158-1525</identifier><identifier>EISBN: 9781424453092</identifier><identifier>EISBN: 1424453097</identifier><identifier>DOI: 10.1109/ISCAS.2010.5537493</identifier><identifier>LCCN: 80-646530</identifier><language>eng</language><publisher>IEEE</publisher><subject>Clocks ; Current-voltage characteristics ; Hysteresis ; Logic gates ; Logic programming ; Neuromorphics ; Reconfigurable logic ; Robustness ; Switches ; Voltage</subject><ispartof>2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.1671-1674</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5537493$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>230,309,310,780,784,789,790,885,2058,4050,4051,27925,54555,54920,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5537493$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttps://research.chalmers.se/publication/125335$$DView record from Swedish Publication Index$$Hfree_for_read</backlink></links><search><creatorcontrib>Chiragwandi, Z</creatorcontrib><creatorcontrib>Sköldberg, J</creatorcontrib><creatorcontrib>Wendin, G</creatorcontrib><title>Robustness of logic gates and reconfigurability of neuromorphic switching networks</title><title>2010 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>Nanoparticle networks with functional molecular links that show current-voltage characteristics (IVC) with negative differential resistance (NDR) can be trained to perform XOR-AND logic gates (Husband et al. [1]; Skoldberg and Wendin [2]). In this work we investigate the robustness of the Nanocell network by removing links until desired logic gates no longer can be configured or operated within our simulation of the network. We present results for the robustness of XOR-AND configured (halfadder) Nanocells, as well as the effects of varying the IVC and NDR characteristics of the linker molecules.</description><subject>Clocks</subject><subject>Current-voltage characteristics</subject><subject>Hysteresis</subject><subject>Logic gates</subject><subject>Logic programming</subject><subject>Neuromorphics</subject><subject>Reconfigurable logic</subject><subject>Robustness</subject><subject>Switches</subject><subject>Voltage</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>1424453089</isbn><isbn>9781424453085</isbn><isbn>9781424453092</isbn><isbn>1424453097</isbn><isbn>9781424453092</isbn><isbn>1424453097</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo9kctuwjAQRd0HUinlB9pNfiDUz8ReItQHElIlaNeW7YyDW0iQHYT4-wZBO5vRnXt1FncQeiR4QghWz_PVbLqaUNxrIVjJFbtCY1VKwinngmFFr9GQEiFzIqi4Qfd_hlS3aIhpSXLOMB2gocR5wYveuUPjlL5xP1zQgpVDtFy2dp-6BlLKWp9t2jq4rDYdpMw0VRbBtY0P9T4aGzahO55CDexju23jbt1n0yF0bh2auj93hzb-pAc08GaTYHzZI_T1-vI5e88XH2_z2XSRBypIl3vmCmOVVAWhWJJSAGZEKc-5koCrCkowknlSYWydEZ4Atsy7yhrKrPKEjdDqzE0H2O2t3sWwNfGoWxN0hAQmurV2a7PZQkw6gbaSY8cJ07yESnNZUG0sdRqg8spV5an1nvp0pgYA-GdeHsB-AX3FdZ4</recordid><startdate>201005</startdate><enddate>201005</enddate><creator>Chiragwandi, Z</creator><creator>Sköldberg, J</creator><creator>Wendin, G</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope><scope>ADTPV</scope><scope>BNKNJ</scope><scope>F1S</scope></search><sort><creationdate>201005</creationdate><title>Robustness of logic gates and reconfigurability of neuromorphic switching networks</title><author>Chiragwandi, Z ; Sköldberg, J ; Wendin, G</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i251t-f3c6ab98961208175e03199f4498e0dde7ea83f1d00bca5f1e0b3fcdba23b9f13</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Clocks</topic><topic>Current-voltage characteristics</topic><topic>Hysteresis</topic><topic>Logic gates</topic><topic>Logic programming</topic><topic>Neuromorphics</topic><topic>Reconfigurable logic</topic><topic>Robustness</topic><topic>Switches</topic><topic>Voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Chiragwandi, Z</creatorcontrib><creatorcontrib>Sköldberg, J</creatorcontrib><creatorcontrib>Wendin, G</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection><collection>SwePub</collection><collection>SwePub Conference</collection><collection>SWEPUB Chalmers tekniska högskola</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chiragwandi, Z</au><au>Sköldberg, J</au><au>Wendin, G</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Robustness of logic gates and reconfigurability of neuromorphic switching networks</atitle><btitle>2010 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2010-05</date><risdate>2010</risdate><spage>1671</spage><epage>1674</epage><pages>1671-1674</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>1424453089</isbn><isbn>9781424453085</isbn><isbn>9781424453092</isbn><isbn>1424453097</isbn><eisbn>9781424453092</eisbn><eisbn>1424453097</eisbn><abstract>Nanoparticle networks with functional molecular links that show current-voltage characteristics (IVC) with negative differential resistance (NDR) can be trained to perform XOR-AND logic gates (Husband et al. [1]; Skoldberg and Wendin [2]). In this work we investigate the robustness of the Nanocell network by removing links until desired logic gates no longer can be configured or operated within our simulation of the network. We present results for the robustness of XOR-AND configured (halfadder) Nanocells, as well as the effects of varying the IVC and NDR characteristics of the linker molecules.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2010.5537493</doi><tpages>4</tpages></addata></record>
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2158-1525
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Clocks
Current-voltage characteristics
Hysteresis
Logic gates
Logic programming
Neuromorphics
Reconfigurable logic
Robustness
Switches
Voltage
title Robustness of logic gates and reconfigurability of neuromorphic switching networks
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T05%3A28%3A37IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-swepub_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Robustness%20of%20logic%20gates%20and%20reconfigurability%20of%20neuromorphic%20switching%20networks&rft.btitle=2010%20IEEE%20International%20Symposium%20on%20Circuits%20and%20Systems%20(ISCAS)&rft.au=Chiragwandi,%20Z&rft.date=2010-05&rft.spage=1671&rft.epage=1674&rft.pages=1671-1674&rft.issn=0271-4302&rft.eissn=2158-1525&rft.isbn=1424453089&rft.isbn_list=9781424453085&rft.isbn_list=9781424453092&rft.isbn_list=1424453097&rft_id=info:doi/10.1109/ISCAS.2010.5537493&rft.eisbn=9781424453092&rft.eisbn_list=1424453097&rft_dat=%3Cswepub_6IE%3Eoai_research_chalmers_se_b840c413_47ed_4862_ab2c_eedf9cd71109%3C/swepub_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i251t-f3c6ab98961208175e03199f4498e0dde7ea83f1d00bca5f1e0b3fcdba23b9f13%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5537493&rfr_iscdi=true