A novel truncated squarer with linear compensation function

A truncated binary squarer is a squarer with a n bit input that produces a n bit output. The proposed design minimizes the mean square error of the squarer and results in a very simple and fast circuital implementation. The squarer, compared against state of the art circuits, provides a reduction of...

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Bibliographic Details
Main Authors: Garofalo, V, Coppola, M, De Caro, D, Napoli, E, Petra, N, Strollo, A G M
Format: Conference Proceeding
Language:English
Subjects:
Adaptive filters
Circuits
Digital arithmetic
Digital signal processing
Frequency
Hardware
Mean square error methods
Power dissipation
Silicon
Vector quantization
Online Access:Request full text
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Summary:A truncated binary squarer is a squarer with a n bit input that produces a n bit output. The proposed design minimizes the mean square error of the squarer and results in a very simple and fast circuital implementation. The squarer, compared against state of the art circuits, provides a reduction of the mean square error ranging from 20% to 5%. At the same time, the proposed squarer is able to reduce the power dissipation, reduce the silicon area occupation, and increase the maximum working frequency. Implementations results are provided for a 0.18μm technology.
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2010.5537591