High throughput area-efficient SoC-based forward/inverse integer transforms for H.264/AVC

In this paper, high throughput area-efficient system-on-chip-based (SoC) forward/inverse integer transform (FIT/IIT) modules for H.264/AVC are proposed. High throughput can be achieved by pipelining quantization/rescaling and FIT/IIT blocks; while efficient area is possible by reusing architecture o...

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Bibliographic Details
Main Authors: Do, T T T, Le, T M
Format: Conference Proceeding
Language:English
Subjects:
Application specific processors
Automatic voltage control
Circuit simulation
Circuit synthesis
Discrete transforms
Hardware
Pipeline processing
Quantization
Throughput
Video compression
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Summary:In this paper, high throughput area-efficient system-on-chip-based (SoC) forward/inverse integer transform (FIT/IIT) modules for H.264/AVC are proposed. High throughput can be achieved by pipelining quantization/rescaling and FIT/IIT blocks; while efficient area is possible by reusing architecture of all four transforms and using buffers for smoothening multiplications and reducing the number of multipliers and quantization/rescaling hardware. With the support of an Application Specific Instruction Processor (ASIP) and 2 built-in-RAM DMACs, the proposed FIT/IIT modules can perform both 4×4 and 8×8 transforms, and 2×2 and 4×4 Hadamard transforms of DC coefficients. Compared to the reported designs in 0.18 μm technology, the proposed FIT and IIT modules score higher Data Throughput per Unit Area (DTUA), and operate on each 8×8 block including I/O in 8 cycles, at 162.1 and 230.9 MHz, respectively.
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2010.5537614