On scalable spiking convnet hardware for cortex-like visual sensory processing systems

• Main Authors: Camuñas-Mesa, L, Pérez-Carrasco, J A, Zamarreño-Ramos, C, Serrano-Gotarredona, T, Linares-Barranco, B
• Format: Conference Proceeding
• Language: English
• Subjects: Hardware
• ISSN: 0271-4302; 2158-1525
• DOI: 10.1109/ISCAS.2010.5537918

This paper summarizes how Convolutional Neural Networks (ConvNets) can be implemented in hardware using Spiking neural network Address-Event-Representation (AER) technology, for sophisticated pattern and object recognition tasks operating at mili second delay throughputs. Although such hardware would require hundreds of individual convolutional modules and thus is presently not yet available, we discuss methods and technologies for implementing it in the near future. On the other hand, we provide precise behavioral simulations of large scale spiking AER convolutional hardware and evaluate its performance, by using performance figures of already available AER convolution chips fed with real sensory data obtained from physically available AER motion retina chips. We provide simulation results of systems trained for people recognition, showing recognition delays of a few miliseconds from stimulus onset. ConvNets show good up scaling behavior and possibilities for being implemented efficiently with new nano scale hybrid CMOS/nonCMOS technologies.