A 5Gb/s pulse signaling interface for low power on-chip data communication

This paper presents an on-chip pulse signaling scheme for low power on-chip interconnection. Both near-end and far-end employ equalization circuits to compensate the high frequency attenuation of long channel. The on-chip data bus is designed by co-planar micro-strip line in Metal 5 and Metal 6 and...

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Bibliographic Details
Main Authors: Hung-Wen Lin, Ying-Chieh Ho, YingLin Fa, ChauChin Su
Format: Conference Proceeding
Language:English
Subjects:
Attenuation
Bit rate
CMOS process
Data communication
Frequency
Hysteresis
Impedance
Integrated circuit interconnections
Inverters
Jitter
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Summary:This paper presents an on-chip pulse signaling scheme for low power on-chip interconnection. Both near-end and far-end employ equalization circuits to compensate the high frequency attenuation of long channel. The on-chip data bus is designed by co-planar micro-strip line in Metal 5 and Metal 6 and with a characteristic impedance of 75 ohm. The receiver uses self-biased inverters and transmission gates to design inductive-peaking and non-clock hysteresis amplifiers. In 0.13um CMOS process, the proposed I/O occupies a total area of 0.07mm 2 . At a bit rate of 5Gbps, the accumulated peak-to-peak jitter of overall I/O system and a 5mm of channel length is 76ps. And it consumes 8mW of power under 1.2V supply voltage or with a power efficiency of 0.32pJ/bit/mm.
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2010.5537978