A 0.23 /spl mu/m/sup 2/ double self-aligned contact cell for gigabit DRAMs with a Ge-added vertical epitaxial Si pad

A new stacked capacitor memory cell with folded bit-line arrangement has been developed using a double self-aligned contact technology. By using a combination of a vertical epitaxial growth Si pad and Si/sub 3/N/sub 4/ caps as etch stop layers on both the bit-lines and word-lines, the cell area usin...

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Main Authors: Koga, H., Kasai, N., Hada, H., Tatsumi, T., Mori, H., Iwao, S., Saino, K., Yamaguchi, H., Nakajima, K., Yamada, Y., Tokunaga, K., Hirasawa, S., Yoshida, K., Nishizawa, A., Hashimoto, T., Ando, K., Kato, Y., Takemura, K., Koyama, K.
Format: Conference Proceeding
Language:English
Subjects:
Capacitors
Controllability
Degradation
Electrodes
Etching
Fabrication
National electric code
Random access memory
Space technology
Wiring
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Summary:A new stacked capacitor memory cell with folded bit-line arrangement has been developed using a double self-aligned contact technology. By using a combination of a vertical epitaxial growth Si pad and Si/sub 3/N/sub 4/ caps as etch stop layers on both the bit-lines and word-lines, the cell area using 0.15 /spl mu/m design rule can be reduced to 0.23 /spl mu/m/sup 2/ with 0.1 /spl mu/m alignment tolerance. Through addition of germanium (Ge) to the Si pad, the controllability of epitaxially grown Si pad features can be improved, resulting in an increase in the growth rate ratio of perpendicular to lateral directions by a factor of 4 and a decrease in resistance of the epi pad from 5 k/spl Omega/ to 1 k/spl Omega/.
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.1996.554052