A low power multiphase all-digital phase locked loop with reusing SAR

This paper presents a low power multiphase all-digital phase locked loop (ADPLL) with reusing successive approximation register (SAR) control. The SAR control unit is reusing both in the coarse and fine stage. The hardware cost and power consumption of reusing SAR control unit is one half of convent...

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Bibliographic Details
Main Author: Pao-Lung Chen
Format: Conference Proceeding
Language:English
Subjects:
Circuit simulation
Clocks
CMOS process
CMOS technology
Communication system control
Energy consumption
Filters
Frequency
Phase locked loops
Voltage-controlled oscillators
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Summary:This paper presents a low power multiphase all-digital phase locked loop (ADPLL) with reusing successive approximation register (SAR) control. The SAR control unit is reusing both in the coarse and fine stage. The hardware cost and power consumption of reusing SAR control unit is one half of conventional SAR control unit. This output frequency of this multiphase phase locked loop works from 102 MHz to 735 MHz. The power consumption of the proposed low power multiphase ADPLL is 3.6 mW at 320 MHz based on post-layout simulation in TSMC 0.18 μm 1P6M CMOS process. The chip's core area is 332μm × 187μm.
DOI:10.1109/ICGCS.2010.5542971