Ultra-thin body Silicon On Insulator and nanowire transistors for 22nm technology node and below

• Main Authors: Poiroux, Thierry, Andrieu, François, Weber, Olivier, Dupre, Cecilia, Ernst, Thomas, Fenouillet-Beranger, Claire, Perreau, Pierre, Buj-Dufournet, Christel, Tosti, Lucie, Brevard, Laurent, Barraud, Sylvain, Faynot, Olivier
• Format: Conference Proceeding
• Language: English
• Subjects: CMOS scaling; Electrostatics; Logic gates; nanowire technology; Scalability; Silicon; Silicon on insulator technology; Threshold voltage; Transistors; variability

We demonstrate that Fully Depleted Silicon-On-Insulator (FDSOI) technology is a simple and mature alternative to the bulk one for the 22nm technology node and beyond. In particular, this technology allows significant improvement of the transistors electrostatic control and variability. Furthermore, the integration of such FDSOI transistors on an ultra-thin buried oxide allows their scalability down to 10nm gate lengths and enables an efficient use of power management techniques. We also illustrate some technological ways to boost the drive current of these devices. Finally, we present a 3D-stacked nanowire architecture as a solution to extend the scaling to the sub-10nm technology nodes and to increase significantly the current supplied per layout unit area.