A dual core oxide 8T SRAM cell with low Vccmin and dual voltage supplies in 45nm triple gate oxide and multi Vt CMOS for very high performance yet low leakage mobile SoC applications

In this work we have demonstrated, for the first time, a 0.605μm 2 dual core oxide (DCO) dual Vdd 8T SRAM cell in 45 LPG triple gate oxide CMOS process for use as L1 cache for high performance low leakage mobile applications. The DCO 8T SRAM operates under dual voltage supplies with write assist. Co...

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Main Authors: Ping Liu, Wang, J, Phan, M, Garg, M, Zhang, R, Cassier, A, Chua-Eoan, L, Andreev, B, Weyland, S, Ekbote, S, Han, M, Fischer, J, Yeap, Geoffrey C.-F, Ping-Wei Wang, Li, Q, Hou, C S, Lee, S B, Wang, Y F, Lin, S S, Cao, M, Mii, Y J
Format: Conference Proceeding
Language:English
Subjects:
Arrays
Logic gates
Mobile communication
Random access memory
Robustness
Transistors
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Summary:In this work we have demonstrated, for the first time, a 0.605μm 2 dual core oxide (DCO) dual Vdd 8T SRAM cell in 45 LPG triple gate oxide CMOS process for use as L1 cache for high performance low leakage mobile applications. The DCO 8T SRAM operates under dual voltage supplies with write assist. Compared to traditional single-end 8T cell, DCO 8T SRAM showed the same performance with only half the standby leakage, and lower Vccmin. The PU Vt and dual core oxide boundary were optimized to achieve robust Vccmin, process margin and reliability. The 45 LPG thin core transistors and the DCO 8T SRAM are able to achieve 1.5 GHz speed with ~500mW at 0.9 V and a low Vccmin of 0.6 V.
ISSN:0743-1562
DOI:10.1109/VLSIT.2010.5556200