8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS

• Main Authors: Witters, L, Takeoka, S, Yamaguchi, S, Hikavyy, A, Shamiryan, D, Cho, M, Chiarella, T, Ragnarsson, L.-A, Loo, R, Kerner, C, Crabbe, Y, Franco, J, Tseng, J, Wang, W E, Rohr, E, Schram, T, Richard, O, Bender, H, Biesemans, S, Absil, P, Hoffmann, T
• Format: Conference Proceeding
• Language: English
• Subjects: Annealing; CMOS; CMOS integrated circuits; dual channel; Logic gates; low EOT; low V t; Metals; MOS devices; SiGe; Silicon; Silicon germanium
• ISSN: 0743-1562
• DOI: 10.1109/VLSIT.2010.5556219

We report low V t (V t,Lg=1μm =±0.26V) high performance CMOS devices with ultra-scaled T inv down to T inv ~8Å using a gate-first dual Si/SiGe channel low-complexity integration approach. Compared to a dual dielectric cap gate-first integration scheme, the devices fabricated with the novel scheme show for the same high-k/metal gate stack (1) 3Å reduction in nMOS and pMOS T inv (2) 220mV lower long channel pMOS V t (3) 21%/12% pMOS/nMOS drive current increase at I off =100nA/μm and (4) 50% improvement in long channel pMOS Vt variability. For a fixed T inv of 12Å, a 4 times higher hole mobility and 350mV increase in NBTI 10years lifetime operating voltage are obtained.