Dynamic Power Management on LDPC Decoders

This paper presents a dynamic power management strategy for the iterative decoding of low-density parity-check (LDPC) codes. We propose an online algorithm for adjusting the operation of a power manageable decoder. Decision making is based upon the monitoring of a convergence metric independent from...

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Main Authors: Amador, Erick, Knopp, Raymond, Rezard, Vincent, Pacalet, Renaud
Format: Conference Proceeding
Language:English
Subjects:
Convergence
Decoding
Estimation
Iterative decoding
Measurement
Switches
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creator Amador, Erick
Knopp, Raymond
Rezard, Vincent
Pacalet, Renaud
description This paper presents a dynamic power management strategy for the iterative decoding of low-density parity-check (LDPC) codes. We propose an online algorithm for adjusting the operation of a power manageable decoder. Decision making is based upon the monitoring of a convergence metric independent from the message computation kernel. Furthermore we analyze the feasibility of a VLSI implementation for such algorithm. Up to 54% savings in energy were achieved with a relatively low loss on error-correcting performance.
doi_str_mv 10.1109/ISVLSI.2010.70
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subjects Convergence
Decoding
Estimation
Iterative decoding
Measurement
Switches
title Dynamic Power Management on LDPC Decoders
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