Stack based module generator for analog MOS circuits

This paper describes a novel method for analog circuit partitioning and MOS transistor stacking. The method is based on a new algorithm dealing with analog specific constraints and on a set of heuristics for stack generation using a pattern database and transistor size trimming. Experimental results...

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Bibliographic Details
Main Authors: Spanoche, S.-A., Arsintescu, G.B.
Format: Conference Proceeding
Language:English
Subjects:
Cost function
Integrated circuit interconnections
Manuals
NP-complete problem
Parasitic capacitance
Partitioning algorithms
Shape
Simulated annealing
Stacking
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Description
Summary:This paper describes a novel method for analog circuit partitioning and MOS transistor stacking. The method is based on a new algorithm dealing with analog specific constraints and on a set of heuristics for stack generation using a pattern database and transistor size trimming. Experimental results show the effectiveness of the method that is described.
DOI:10.1109/SMICND.1996.557324