Towards a parameterizable cycle-accurate ISS in ArchC

With the increase in the design complexity of MP-SoC architectures, flexible and accurate processor simulators became a necessity for exploring the vast design space solutions. In this paper, we present a flexible cycle-accurate ISS model based on ArchC 2.0 language. The model can have a variable pi...

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Bibliographic Details
Main Authors: Bechara, C, Ventroux, N, Etiemble, D
Format: Conference Proceeding
Language:English
Subjects:
ADL
Computational modeling
Computer architecture
cycle-accurate
Design Space Exploration
Hazards
ISS
Pipelines
Registers
Synchronization
System-on-a-chip
System-on-Chip
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Description
Summary:With the increase in the design complexity of MP-SoC architectures, flexible and accurate processor simulators became a necessity for exploring the vast design space solutions. In this paper, we present a flexible cycle-accurate ISS model based on ArchC 2.0 language. The model can have a variable pipeline depth and can be integrated easily in any SoC design based on SystemC. Its performance and capabilities are demonstrated by running MiBench embedded benchmark suite, while extracting pipeline statistics for each application.
ISSN:2161-5322
2161-5330
DOI:10.1109/AICCSA.2010.5586945