A Low-Power Fast-Transient 90-nm Low-Dropout Regulator With Multiple Small-Gain Stages

• Published in: IEEE journal of solid-state circuits 2010-11, Vol.45 (11), p.2466-2475
• Main Authors: Ho, Marco, Ka Nang Leung, Ki-Leung Mak
• Format: Article
• Language: English
• Subjects: Applied sciences; Bandwidth; Capacitance; Capacitors; Circuit properties; Circuits; Control; Design. Technologies. Operation analysis. Testing; Dielectric, amorphous and glass solid devices; Electric potential; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Gain; Integrated circuits; Low-dropout regulator (LDO); Nanoscale devices; nanoscale integrated circuits; Poles; Poles and zeros; Regulators; Rejection; Resistance; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; small-gain stages; Transistors; Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2010.2072611

A power-efficient 90-nm low-dropout regulator (LDO) with multiple small-gain stages is proposed in this paper. The proposed channel-resistance-insensitive small-gain stages provide loop gain enhancements without introducing low-frequency poles before the unity-gain frequency (UGF). As a result, both the loop gain and bandwidth of the LDO are improved, so that the accuracy and response speed of voltage regulation are significantly enhanced. As no on-chip compensation capacitor is required, the active chip area of the LDO is only 72.5 μm × 37.8 μm. Experimental results show that the LDO is capable of providing an output of 0.9 V with maximum output current of 50 mA from a 1-V supply. The LDO has a quiescent current of 9.3 μA, and has significantly improvement in line and load transient responses as well as performance in power-supply rejection ratio (PSRR).