A 5 mm ^ 40 nm LP CMOS Transceiver for a Software-Defined Radio Platform

A 5 mm 2 transceiver front-end suitable for a software-defined radio (SDR) platform is implemented in a 40-nm LP digital CMOS technology. Tailored for all modern communication standards relevant for a modern handheld mobile device (2G/3G/4G cellular, WLAN, Bluetooth, GPS, broadcasting, etc.), it use...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2010-12, Vol.45 (12), p.2794-2806
Main Authors: Ingels, M, Giannini, V, Borremans, J, Mandal, G, Debaillie, B, Van Wesemael, P, Sano, T, Yamamoto, T, Hauspie, D, Van Driessche, J, Craninckx, J
Format: Article
Language:English
Subjects:
CMOS
CMOS technology
Long Term Evolution
LTE
Mixers
Radio frequency
receiver
Receivers
SAW-less
SDR
software defined radio
Software radio
transceiver
Transceivers
transmitter
Transmitters
WCDMA
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Summary:A 5 mm 2 transceiver front-end suitable for a software-defined radio (SDR) platform is implemented in a 40-nm LP digital CMOS technology. Tailored for all modern communication standards relevant for a modern handheld mobile device (2G/3G/4G cellular, WLAN, Bluetooth, GPS, broadcasting, etc.), it uses radio architectures and circuits that ensure flexible performance at a minimal cost in area and power consumption. The receive section features four parallel LNAs to cover the frequency range from 100 MHz up to 6 GHz, a 25 % duty cycle passive mixer with IIP2 calibration, fifth-order baseband filtering up to 20 MHz, variable-gain amplification, and a 10-b 65 MS/s 34 fj/conv-step SAR ADC. It achieves NF down to 2.4 dB, more than 30-dB EVM and 50-dBm IIP2. In the transmit section, main emphasis is given to the out-of-band noise requirement that enables SAW-less operation in FDD systems: a flexible reconstruction filter is followed by a voltage-sampling mixer and a variable gain PPA. The TX chain achieves 3.2% EVM at 0-dBm output power, with CNR down to-156 dBc/Hz. For frequency synthesis, two dual-VCO 5.9-12.8 GHz fractional-N PLLs are implemented together with a chain of divide-by-2 circuits for quadrature generation.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2010.2075210