0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS

Digital LDO is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5V, the digital LDO eliminates all analog circuits and is controlled by dig...

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Main Authors: Okuma, Yasuyuki, Ishida, Koichi, Ryu, Yoshikatsu, Xin Zhang, Po-Hung Chen, Watanabe, Kazunori, Takamiya, Makoto, Sakurai, Takayasu
Format: Conference Proceeding
Language:English
Subjects:
Bidirectional control
Clocks
CMOS integrated circuits
Current measurement
Shift registers
Switches
Transient analysis
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creator Okuma, Yasuyuki
Ishida, Koichi
Ryu, Yoshikatsu
Xin Zhang
Po-Hung Chen
Watanabe, Kazunori
Takamiya, Makoto
Sakurai, Takayasu
description Digital LDO is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-μA quiescent current at 200-μA load current. Both the input voltage and the quiescent current are the lowest values in the published LDO's, which indicates the good energy efficiency of the digital LDO at 0.5-V operation.
doi_str_mv 10.1109/CICC.2010.5617586
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Bidirectional control
Clocks
CMOS integrated circuits
Current measurement
Shift registers
Switches
Transient analysis
title 0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS
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