Glitch-induced within-die variations of dynamic energy in voltage-scaled nano-CMOS circuits

• Main Authors: Kamel, D, Hocquet, C, Standaert, François-Xavier, Flandre, D, Bol, D
• Format: Conference Proceeding
• Language: eng ; jpn
• Subjects: Capacitance; CMOS integrated circuits; Delay; Integrated circuit modeling; Logic gates; Ring oscillators; Semiconductor device measurement
• ISSN: 1930-8833; 2643-1319
• DOI: 10.1109/ESSCIRC.2010.5619757

Variability strongly impacts performances of nanometer CMOS digital circuits. In this paper, we experimentally study the effects of variability on dynamic energy consumption of 65nm logic circuits, considering deep voltage scaling for low-power applications. While we confirm that variations in dynamic energy at 1V are small and dominated by die-to-die correlated capacitance fluctuations, we report for the first time that within-die uncorrelated delay variability magnifies dynamic energy variations at lower voltages by a factor 5×. Indeed, random glitches are generated by variability-induced unbalanced logic paths, which affect the activity factor of combinatorial circuits. The associated normalized dynamic power variations at 0.4V are comparable to die-to-die leakage power variations.