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Improved ESD protection in advanced FDSOI by using hybrid SOI/bulk Co-integration
We investigate the influence of different technological parameters on ESD robustness in advanced FDSOI devices. From Transmission Line Pulse (TLP) measurements, a comparison with other technologies enables us to evaluate the impact of ultrathin film and buried oxide. A solution based on hybrid SOI/b...
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creator | Benoist, T Fenouillet-Beranger, C Guitard, N Huguenin, J.-L Monfray, S Galy, P Buj, C Andrieu, F Perreau, P Marin-Cudraz, D Faynot, O Cristoloveanu, S Gentil, P |
description | We investigate the influence of different technological parameters on ESD robustness in advanced FDSOI devices. From Transmission Line Pulse (TLP) measurements, a comparison with other technologies enables us to evaluate the impact of ultrathin film and buried oxide. A solution based on hybrid SOI/bulk co-integration by using Silicon-On-Nothing technology is presented in order to improve ultra-thin film ESD performance. |
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fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5623728</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5623728</ieee_id><sourcerecordid>5623728</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-8bd019624f9c622cbc96bb86f6aacf7be35305b1aca7ee27276497c092f804eb3</originalsourceid><addsrcrecordid>eNotjM1KAzEcxONBUGufwEteYDHfH0fZtrpQKFI9lyT7T4222ZLdFvbtXalzmeE3zNygByqN5Joaxu_QvO-_ySQpDRPiHr03x1PpLtDi5XaBpzhAGFKXccrYtReXw1StFttNg_2Iz33Ke_w1-pJaPLFnfz784LqrUh5gX9zf8hHdRnfoYf7vM_S5Wn7Ub9V689rUL-sqUS2HyviWUKuYiDYoxoIPVnlvVFTOhag9cMmJ9NQFpwGYZloJqwOxLBoiwPMZerr-JgDYnUo6ujLupGJcM8N_AXwLR6I</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Improved ESD protection in advanced FDSOI by using hybrid SOI/bulk Co-integration</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Benoist, T ; Fenouillet-Beranger, C ; Guitard, N ; Huguenin, J.-L ; Monfray, S ; Galy, P ; Buj, C ; Andrieu, F ; Perreau, P ; Marin-Cudraz, D ; Faynot, O ; Cristoloveanu, S ; Gentil, P</creator><creatorcontrib>Benoist, T ; Fenouillet-Beranger, C ; Guitard, N ; Huguenin, J.-L ; Monfray, S ; Galy, P ; Buj, C ; Andrieu, F ; Perreau, P ; Marin-Cudraz, D ; Faynot, O ; Cristoloveanu, S ; Gentil, P</creatorcontrib><description>We investigate the influence of different technological parameters on ESD robustness in advanced FDSOI devices. From Transmission Line Pulse (TLP) measurements, a comparison with other technologies enables us to evaluate the impact of ultrathin film and buried oxide. A solution based on hybrid SOI/bulk co-integration by using Silicon-On-Nothing technology is presented in order to improve ultra-thin film ESD performance.</description><identifier>EISBN: 1585371823</identifier><identifier>EISBN: 9781585371822</identifier><language>eng</language><publisher>IEEE</publisher><subject>Conductivity ; Electric fields ; Electrostatic discharge ; Leakage current ; Logic gates ; Robustness ; Silicon</subject><ispartof>Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010, 2010, p.1-6</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5623728$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5623728$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Benoist, T</creatorcontrib><creatorcontrib>Fenouillet-Beranger, C</creatorcontrib><creatorcontrib>Guitard, N</creatorcontrib><creatorcontrib>Huguenin, J.-L</creatorcontrib><creatorcontrib>Monfray, S</creatorcontrib><creatorcontrib>Galy, P</creatorcontrib><creatorcontrib>Buj, C</creatorcontrib><creatorcontrib>Andrieu, F</creatorcontrib><creatorcontrib>Perreau, P</creatorcontrib><creatorcontrib>Marin-Cudraz, D</creatorcontrib><creatorcontrib>Faynot, O</creatorcontrib><creatorcontrib>Cristoloveanu, S</creatorcontrib><creatorcontrib>Gentil, P</creatorcontrib><title>Improved ESD protection in advanced FDSOI by using hybrid SOI/bulk Co-integration</title><title>Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010</title><addtitle>EOSESD</addtitle><description>We investigate the influence of different technological parameters on ESD robustness in advanced FDSOI devices. From Transmission Line Pulse (TLP) measurements, a comparison with other technologies enables us to evaluate the impact of ultrathin film and buried oxide. A solution based on hybrid SOI/bulk co-integration by using Silicon-On-Nothing technology is presented in order to improve ultra-thin film ESD performance.</description><subject>Conductivity</subject><subject>Electric fields</subject><subject>Electrostatic discharge</subject><subject>Leakage current</subject><subject>Logic gates</subject><subject>Robustness</subject><subject>Silicon</subject><isbn>1585371823</isbn><isbn>9781585371822</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotjM1KAzEcxONBUGufwEteYDHfH0fZtrpQKFI9lyT7T4222ZLdFvbtXalzmeE3zNygByqN5Joaxu_QvO-_ySQpDRPiHr03x1PpLtDi5XaBpzhAGFKXccrYtReXw1StFttNg_2Iz33Ke_w1-pJaPLFnfz784LqrUh5gX9zf8hHdRnfoYf7vM_S5Wn7Ub9V689rUL-sqUS2HyviWUKuYiDYoxoIPVnlvVFTOhag9cMmJ9NQFpwGYZloJqwOxLBoiwPMZerr-JgDYnUo6ujLupGJcM8N_AXwLR6I</recordid><startdate>201010</startdate><enddate>201010</enddate><creator>Benoist, T</creator><creator>Fenouillet-Beranger, C</creator><creator>Guitard, N</creator><creator>Huguenin, J.-L</creator><creator>Monfray, S</creator><creator>Galy, P</creator><creator>Buj, C</creator><creator>Andrieu, F</creator><creator>Perreau, P</creator><creator>Marin-Cudraz, D</creator><creator>Faynot, O</creator><creator>Cristoloveanu, S</creator><creator>Gentil, P</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201010</creationdate><title>Improved ESD protection in advanced FDSOI by using hybrid SOI/bulk Co-integration</title><author>Benoist, T ; Fenouillet-Beranger, C ; Guitard, N ; Huguenin, J.-L ; Monfray, S ; Galy, P ; Buj, C ; Andrieu, F ; Perreau, P ; Marin-Cudraz, D ; Faynot, O ; Cristoloveanu, S ; Gentil, P</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-8bd019624f9c622cbc96bb86f6aacf7be35305b1aca7ee27276497c092f804eb3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Conductivity</topic><topic>Electric fields</topic><topic>Electrostatic discharge</topic><topic>Leakage current</topic><topic>Logic gates</topic><topic>Robustness</topic><topic>Silicon</topic><toplevel>online_resources</toplevel><creatorcontrib>Benoist, T</creatorcontrib><creatorcontrib>Fenouillet-Beranger, C</creatorcontrib><creatorcontrib>Guitard, N</creatorcontrib><creatorcontrib>Huguenin, J.-L</creatorcontrib><creatorcontrib>Monfray, S</creatorcontrib><creatorcontrib>Galy, P</creatorcontrib><creatorcontrib>Buj, C</creatorcontrib><creatorcontrib>Andrieu, F</creatorcontrib><creatorcontrib>Perreau, P</creatorcontrib><creatorcontrib>Marin-Cudraz, D</creatorcontrib><creatorcontrib>Faynot, O</creatorcontrib><creatorcontrib>Cristoloveanu, S</creatorcontrib><creatorcontrib>Gentil, P</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library Online</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Benoist, T</au><au>Fenouillet-Beranger, C</au><au>Guitard, N</au><au>Huguenin, J.-L</au><au>Monfray, S</au><au>Galy, P</au><au>Buj, C</au><au>Andrieu, F</au><au>Perreau, P</au><au>Marin-Cudraz, D</au><au>Faynot, O</au><au>Cristoloveanu, S</au><au>Gentil, P</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Improved ESD protection in advanced FDSOI by using hybrid SOI/bulk Co-integration</atitle><btitle>Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010</btitle><stitle>EOSESD</stitle><date>2010-10</date><risdate>2010</risdate><spage>1</spage><epage>6</epage><pages>1-6</pages><eisbn>1585371823</eisbn><eisbn>9781585371822</eisbn><abstract>We investigate the influence of different technological parameters on ESD robustness in advanced FDSOI devices. From Transmission Line Pulse (TLP) measurements, a comparison with other technologies enables us to evaluate the impact of ultrathin film and buried oxide. A solution based on hybrid SOI/bulk co-integration by using Silicon-On-Nothing technology is presented in order to improve ultra-thin film ESD performance.</abstract><pub>IEEE</pub><tpages>6</tpages></addata></record> |
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ispartof | Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010, 2010, p.1-6 |
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language | eng |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Conductivity Electric fields Electrostatic discharge Leakage current Logic gates Robustness Silicon |
title | Improved ESD protection in advanced FDSOI by using hybrid SOI/bulk Co-integration |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-20T17%3A38%3A46IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Improved%20ESD%20protection%20in%20advanced%20FDSOI%20by%20using%20hybrid%20SOI/bulk%20Co-integration&rft.btitle=Electrical%20Overstress/Electrostatic%20Discharge%20Symposium%20Proceedings%202010&rft.au=Benoist,%20T&rft.date=2010-10&rft.spage=1&rft.epage=6&rft.pages=1-6&rft_id=info:doi/&rft.eisbn=1585371823&rft.eisbn_list=9781585371822&rft_dat=%3Cieee_6IE%3E5623728%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i175t-8bd019624f9c622cbc96bb86f6aacf7be35305b1aca7ee27276497c092f804eb3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5623728&rfr_iscdi=true |