Non-planar device architecture for 15nm node: FinFET or trigate?

Multi-gate FETs (MuG-FET) such as FinFETs and Trigate FETs have emerged as the most promising candidates to extend the CMOS scaling beyond sub-22nm node. The multi-gate structure has better short channel behaviors due to enhanced electrostatic control from the multiple gates. However, the superior e...

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Bibliographic Details
Main Authors: Chung-Hsun Lin, Chang, J, Guillorn, M, Bryant, A, Oldiges, P, Haensch, W
Format: Conference Proceeding
Language:English
Subjects:
Electrostatics
FinFETs
Logic gates
Parasitic capacitance
Performance evaluation
Resistance
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Summary:Multi-gate FETs (MuG-FET) such as FinFETs and Trigate FETs have emerged as the most promising candidates to extend the CMOS scaling beyond sub-22nm node. The multi-gate structure has better short channel behaviors due to enhanced electrostatic control from the multiple gates. However, the superior electrostatic control of the MuG-FET will be offset by the parasitic gate-to-source/drain capacitance (C gs ). Careful device design and optimization of MuG-FET are necessary to achieve an overall performance advantage over conventional planar technology. In this paper, we evaluated the FinFET and Trigate at 15nm node dimension with consideration of electrostatic behavior, parasitic capacitance and resistance using wellcalibrated TCAD simulations.
ISSN:1078-621X
2577-2295
DOI:10.1109/SOI.2010.5641060