Digital Calibration of Capacitor Mismatch in Sigma-Delta Modulators

This paper presents a capacitor mismatch calibration technique in multibit discrete-time sigma-delta (ΣΔ) modulators based on a capacitor error model, including nonideal integrator gain errors. This model enables the compensation of mismatch-induced nonlinear memory errors in conversion using a simp...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2011-04, Vol.58 (4), p.690-698
Main Authors: Lee, Seung-Chul, Chiu, Yun
Format: Article
Language:English
Subjects:
adaptive digital calibration
analog-to-digital converter (ADC)
Calibration
capacitor mismatch
Capacitors
Circuits
Conversion
digital-to-analog converter (DAC)
Dynamic range
Errors
Gain
Mathematical model
Modulation
Modulators
Noise
nonlinearity
Pseudorandom
Sigma \Delta modulator
Simulation
Switches
test signal
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Summary:This paper presents a capacitor mismatch calibration technique in multibit discrete-time sigma-delta (ΣΔ) modulators based on a capacitor error model, including nonideal integrator gain errors. This model enables the compensation of mismatch-induced nonlinear memory errors in conversion using a simple flnite impulse-response structure. Single-bit pseudorandom noise (PN) is utilized to identify the error coefficients, and an analog-domain PN removal technique is devised to minimize the input signal dynamic-range loss due to the PN circulation in the ΣΔ loop. The behavioral simulation demonstrates that the proposed scheme effectively compensates for the multibit capacitor mismatch errors in the first- and second-order ΣΔ modulators.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2010.2073870