A wavelet image coder and hardware

Presents the hardware implementation of a wavelet image coder. It proposes the architectures to achieve 2-D Discrete Wavelet Transform (DWT) and a fast zerotree image coding (FZIC). The Verilog HDL models for 2-D DWT and FZIC are programmed, and extensive simulation has been carried out to optimize...

Full description

Saved in:
Bibliographic Details
Main Authors: Wenju Gao, Yueou Ren, Qiuju Li, Hongyu Wang, Ting Ai
Format: Conference Proceeding
Language:English
Subjects:
Axles
discrete wavelet transform
Discrete wavelet transforms
verilog HDL
VLSI
zerotree image coding
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Presents the hardware implementation of a wavelet image coder. It proposes the architectures to achieve 2-D Discrete Wavelet Transform (DWT) and a fast zerotree image coding (FZIC). The Verilog HDL models for 2-D DWT and FZIC are programmed, and extensive simulation has been carried out to optimize the design. The completed design is synthesized to Altera CPLD.
DOI:10.1109/BICTA.2010.5645243