Reconfigurable router for dynamic Networks-on-Chip

A reconfigurable router architecture for dynamic Networks-on-Chip (DyNoC) is presented. Dynamically placed modules cover several processing elements and routers of the DyNoC. These processing elements communicate over a second communication level using direct-links between neighbouring elements. Rou...

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Bibliographic Details
Main Authors: Mahr, P, Bobda, C
Format: Conference Proceeding
Language:English
Subjects:
Memory management
Random access memory
Routing
Switching circuits
Table lookup
Timing
Online Access:Request full text
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Description
Summary:A reconfigurable router architecture for dynamic Networks-on-Chip (DyNoC) is presented. Dynamically placed modules cover several processing elements and routers of the DyNoC. These processing elements communicate over a second communication level using direct-links between neighbouring elements. Routers covered by modules are therefore useless. In this paper, several possibilities to use the router as additional resources to enhance complexity of modules are presented. The reconfigurable router is evaluated in terms of area, speed and latencies. A case-study where the router is used as a lookup-table demonstrates the feasibility of this approach.
ISSN:2150-5500
2150-5519
DOI:10.1109/RSP.2010.5656341