FFT Implementation with Fused Floating-Point Operations

This paper describes two fused floating-point operations and applies them to the implementation of fast Fourier transform (FFT) processors. The fused operations are a two-term dot product and an add-subtract unit. The FFT processors use "butterfly" operations that consist of multiplication...

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Bibliographic Details
Published in:IEEE transactions on computers 2012-02, Vol.61 (2), p.284-288
Main Authors: Swartzlander, Earl E., Saleh, H. H. M.
Format: Article
Language:English
Subjects:
Adders
Butterflies
Clocks
Computer simulation
Delay
fast Fourier transform
Fast Fourier transforms
Floating point arithmetic
Fourier transforms
fused floating-point operations
Mathematical models
Multiplication
Processors
Program processors
Radix-2 FFT butterfly
Radix-4 FFT butterfly
Signal processing algorithms
Throughput
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Summary:This paper describes two fused floating-point operations and applies them to the implementation of fast Fourier transform (FFT) processors. The fused operations are a two-term dot product and an add-subtract unit. The FFT processors use "butterfly" operations that consist of multiplications, additions, and subtractions of complex valued data. Both radix-2 and radix-4 butterflies are implemented efficiently with the two fused floating-point operations. When placed and routed using a high performance standard cell technology, the fused FFT butterflies are about 15 percent faster and 30 percent smaller than a conventional implementation. Also the numerical results of the fused implementations are slightly more accurate, since they use fewer rounding operations.
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2010.271