SoC design verification infrastructure

The testing and verification technology for system HDL models, focused to the significant improvement of the quality of design components for digital systems on chips and reduction the development time (time-to-market) by using the simulation environment, testable analysis of the logical structure H...

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Bibliographic Details
Main Authors: Gharibi, W, Hahanov, V
Format: Conference Proceeding
Language:English
Subjects:
Controllability
Engines
Integrated circuit modeling
Observability
Registers
Software
Testing
Online Access:Request full text
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Description
Summary:The testing and verification technology for system HDL models, focused to the significant improvement of the quality of design components for digital systems on chips and reduction the development time (time-to-market) by using the simulation environment, testable analysis of the logical structure HDL-program and the optimal placement of assertion engine is proposed.
DOI:10.1109/SM2ACD.2010.5672359