A 2 GHz 12-bit digital-to-analog converter for direct digital synthesis applications

• Main Authors: Schaffer, T.A., Warren, H.P., Bustamante, M.J., Kong, K.W.
• Format: Conference Proceeding
• Language: English
• Subjects: Clocks; Complexity theory; Design optimization; Digital-analog conversion; Frequency; Laboratories; Lattices; Power dissipation; Synthesizers; Test equipment
• ISSN: 1064-7775; 2379-5638
• DOI: 10.1109/GAAS.1996.567646

A 2 GHz 12-bit digital-to-analog converter (DAC) designed for use in a Direct Digital Synthesizer was demonstrated with spurious performance exceeding -60 dBc when synthesizing 1/8th of a 1 GHz clock. This exceeds the best documented results of which we are aware by more than 15 dB at this clock rate and fractional frequency. When synthesizing near 1/3rd the clock rate the carrier-adjacent spurious performance exceeds -58 dBc at a 1 GHz clock rate, exceeding the 500 MHz clock rate performance of other DACs we have evaluated by 5-10 dB. Although designed to operate well above 2 GHz, state-of-the-art test equipment limited full characterization of the device to a 1 GHz clock rate at the time of evaluation. Unlike that observed with other DACs, nearly constant measured performance versus clock rate up to 1 GHz promises sustained performance at higher clock rates. The 12 bit DAC architecture consists of the 3 most significant bits driving 7 equally weighted current segments while the remaining 9 bits drive identical current segments combined through a binary R2R ladder. This architecture represents the best tradeoff between performance considerations and circuit complexity. The primary focus on this first design iteration was on achieving good spurious performance with less emphasis on power dissipation and on providing key information for a subsequent design optimization. The DAC was fabricated using an integrated circuit process developed at Hughes Research Laboratories and consists of 1200 AlInAs/GaInAs HBTs lattice matched to an InP substrate. The smallest InP-based HBTs utilized emitters having 2/spl times/2 sq. micron emitters with Ft=75 GHz and Fmax=85 GHz. The high speed DAC dissipated 2.8 W.