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Programming efficiency and drain disturb trade-off in embedded Non Volatile Memories
The embedded NOR-type Non Volatile Memory (eNVM) cell is characterized by many figures of merit. Of particular interest are the programming efficiency (PE), defined as the electron gate-to-drain current ratio (I g /I d ) during programming, and the drain disturb current (DDC), defined as the hole ga...
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| creator | Zaka, A Palestri, P Rideau, D Iellina, M Dornel, E Rafhay, Q Tavernier, C Jaouen, H |
| description | The embedded NOR-type Non Volatile Memory (eNVM) cell is characterized by many figures of merit. Of particular interest are the programming efficiency (PE), defined as the electron gate-to-drain current ratio (I g /I d ) during programming, and the drain disturb current (DDC), defined as the hole gate current I gh during drain disturb (Fig. 1). eNVM gate-length scaling has brought shallower and steeper Source/Drain (S/D) junctions enabling not only higher PE but also increased DDC, the latter yielding to potential reliability issues. Therefore, in the spirit of a compromise in channel/LDD implant conditions is here presented, showing a trade-off between electron and hole injection during programming and drain disturb phases, respectively. |
| doi_str_mv | 10.1109/IWCE.2010.5677949 |
| format | conference_proceeding |
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| subjects | Doping Junctions Logic gates Monte Carlo methods Programming Semiconductor process modeling |
| title | Programming efficiency and drain disturb trade-off in embedded Non Volatile Memories |
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