A robust reconfigurable logic device based on less configuration memory logic cell

• Main Authors: Qian Zhao, Ichinomiya, Yoshihiro, Okamoto, Yasuhiro, Amagasaki, Motoki, Iida, Masahiro, Sueyoshi, Toshinori
• Format: Conference Proceeding
• Language: English
• Subjects: Field programmable gate arrays; Logic functions; Memory management; Microprocessors; Table lookup; Tunneling magnetoresistance
• DOI: 10.1109/FPT.2010.5681775

As the size of integrated circuit has reached the nanoscale, embedded memories are more sensitive to single event upset (SEU), because of their low threshold voltage. In particular field-programmable gate arrays (FPGAs), which contain large amounts of configuration memories to implement customer circuits, are more likely to suffer from soft errors caused by SEU. In this research, we first develop a Hamming code based error detect and correct (EDC) circuit that can prevent the configuration memory of a reconfigurable device from SEU. We then propose a novel reconfigurable logic element, namely COGRE, which will use much less configuration memory than the conventional FPGA 4-, 5- or 6-LUTs (lookup tables). Evaluation revealed that compared to the 6-LUT FPGAs with triple modular redundancy (TMR) configuration memory blocks, the 5- and 6-input proposed architecture save about 75.44 and 74.29% memories on average, respectively. And the dependability of the proposed architectures is about 6.8 to 10 times better than the LUTs with a tile level TMR structure on average. Moreover, with the consideration of the on the fly scrubbing advantage of the EDC, SEUs cannot be accumulated, so a much higher dependability can be achieved.