An all digital time amplifier with interpolation scheme for low gain variation

An all digital time amplifier (TA) is proposed in 0.13 μm CMOS process. The TA is based on quantization scheme; hence it guarantees large input range. An interpolation scheme is employed to achieve more than 2 times reduction in gain variation of the TA over the input range. The all digital TA is po...

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Bibliographic Details
Main Authors: Dhar, D, Young-Ho Kwak, Inhwa Jung, Chulwoo Kim
Format: Conference Proceeding
Language:English
Subjects:
All Digital Time Amplifier
Clocks
CMOS integrated circuits
Delay
Interpolation
Logic gates
MOS devices
Signal resolution
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Summary:An all digital time amplifier (TA) is proposed in 0.13 μm CMOS process. The TA is based on quantization scheme; hence it guarantees large input range. An interpolation scheme is employed to achieve more than 2 times reduction in gain variation of the TA over the input range. The all digital TA is portable to other process technology with smaller design effort. The TA shows a gain variation of less than 5% and consumes a power of 14 mW.
DOI:10.1109/SOCDC.2010.5682917