An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier

• Main Authors: Baesler, M, Voigt, S, Teufel, T
• Format: Conference Proceeding
• Language: English
• Subjects: Adders; Computer architecture; decimal; Estimation; Field programmable gate arrays; floating-point; FPGA; IEEE 754-2008; Multiplexing; multiplier; Pipeline processing; Shift registers
• ISSN: 1946-147X; 1946-1488
• DOI: 10.1109/FPL.2010.98

Decimal floating point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, scientific, commercial, and financial applications. In this paper we present an IEEE 754-2008 compliant parallel decimal floating-point multiplier designed to exploit the features of Virtex-5 FPGAs. It is an extension to a previously published decimal fixed-point multiplier. The decimal floating-point multiplier implements early estimation of the shift-left amount and efficient decimal rounding. Additionally, it provides all required rounding modes, exception handling, overflow, and gradual underflow. Several pipeline stages can be added to increase throughput. Furthermore, different modifications are analyzed including shifting by means of hard-wired multipliers and delayed carry propagation adders.