Task Superscalar: An Out-of-Order Task Pipeline

• Main Authors: Etsion, Yoav, Cabarcas, Felipe, Rico, Alejandro, Ramirez, Alex, Badia, Rosa M., Ayguade, Eduard, Labarta, Jesus, Valero, Mateo
• Format: Conference Proceeding
• Language: English
• Subjects: Arquitectura de computadors; Arquitectures paral·leles; CMP/manycore; Computer systems organization > Architectures > Parallel architectures > Multiple instruction, multiple data; Computer systems organization > Dependable and fault-tolerant systems and networks; Data structures; Decoding; Estructures de dades (Informàtica); General and reference > Cross-computing tools and techniques > Performance; Hardware > Integrated circuits; Informàtica; Kernel; Networks > Network performance evaluation; Out-of-order execution; parallel programming; Parallel programming (Computer science); Pipelines; Program processors; Programació paral·lela (Informàtica); Programming; Registers; Runtime; Task analysis; task superscalar; Àrees temàtiques de la UPC
• ISSN: 1072-4451
• DOI: 10.1109/MICRO.2010.13

We present \emph{Task Super scalar}, an abstraction of instruction-level out-of-order pipeline that operates at the task-level. Like ILP pipelines, which uncover parallelism in a sequential instruction stream, task super scalar uncovers task-level parallelism among tasks generated by a sequential thread. Utilizing intuitive programmer annotations of task inputs and outputs, the task super scalar pipeline dynamically detects inter-task data dependencies, identifies task-level parallelism, and executes tasks out-of-order. Furthermore, we propose a design for a distributed task super scalar pipeline front end, that can be embedded into any many core fabric, and manages cores as functional units. We show that our proposed mechanism is capable of driving hundreds of cores simultaneously with non-speculative tasks, which allows our pipeline to sustain work windows consisting of tens of thousands of tasks. We further show that our pipeline can maintain a decode rate faster than 60ns per task and dynamically uncover data dependencies among as many as \tilde 50,000 in-flight tasks, using 7MB of on-chip eDRAM storage. This configuration achieves speedups of 95–255x (average 183x) over sequential execution for nine scientific benchmarks, running on a simulated CMP with 256 cores. Task super scalar thus enables programmers to exploit many core systems effectively, while simultaneously simplifying their programming model.