Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond

Recent device developments and achievements have demonstrated that planar undoped channel Fully depleted SOI devices are becoming a serious alternative to Bulk technologies for 20nm node and below. We have proven this planar option to be easier to integrate than the non planar devices like FinFET. T...

Full description

Saved in:
Bibliographic Details
Main Authors: Faynot, O, Andrieu, F, Weber, O, Fenouillet-Béranger, C, Perreau, P, Mazurier, J, Benoist, T, Rozeau, O, Poiroux, T, Vinet, M, Grenouillet, L, Noel, J.-P, Posseme, N, Barnola, S, Martin, F, Lapeyre, C, Cassé, M, Garros, X, Jaud, M.-A, Thomas, O, Cibrario, G, Tosti, L, Brevard, L, Tabone, C, Gaud, P, Barraud, S, Ernst, T, Deleonibus, S
Format: Conference Proceeding
Language:eng ; jpn
Subjects:
Electrostatics
FinFETs
Logic gates
Materials
Performance evaluation
Scalability
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Recent device developments and achievements have demonstrated that planar undoped channel Fully depleted SOI devices are becoming a serious alternative to Bulk technologies for 20nm node and below. We have proven this planar option to be easier to integrate than the non planar devices like FinFET. This paper gives an overview of the main advantages provided by this technology, as well as the key challenges that need to be addressed. Electrostatic integrity, drivability, within wafer variability and scalability are addressed through silicon data (down to 18nm gate length) and TCAD analyses. Solutions to the Multiple V T challenges and non logic devices (ESD, I/Os) are also reported.
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2010.5703287