Enabling 3X nm DRAM: Record low leakage 0.4 nm EOT MIM capacitors with novel stack engineering

We report the lowest leakage achieved to date in sub-0.5 nm EOT MIM capacitors compatible with DRAM flows, showing for the first time a path enabling scalability to the 3X nm node. A novel stack engineering consisting of: 1) novel controlled ultrathin Ru oxidation process, 2) TiO x interface layer,...

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Main Authors: Pawlak, M A, Popovici, M, Swerts, J, Tomida, K, Min-Soo Kim, Kaczer, B, Opsomer, K, Schaekers, M, Favia, P, Bender, H, Vrancken, C, Govoreanu, B, Demeurisse, C, Wan-Chih Wang, Afanas'ev, V V, Debusschere, I, Altimime, L, Kittl, J A
Format: Conference Proceeding
Language:English
Subjects:
Annealing
Crystallization
Oxidation
Random access memory
Strontium
Tin
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Summary:We report the lowest leakage achieved to date in sub-0.5 nm EOT MIM capacitors compatible with DRAM flows, showing for the first time a path enabling scalability to the 3X nm node. A novel stack engineering consisting of: 1) novel controlled ultrathin Ru oxidation process, 2) TiO x interface layer, is used for the first time to achieve record low Jg-EOT in MIM capacitors using ALD Sr-rich STO high-k dielectric and thin Ru bottom electrode. Record low Jg of 10 -6 A/cm 2 (10 -8 A/cm 2 ) is achieved for EOT of 0.4 nm (0.5 nm) at 0.8 V. Our data is compared favorably (>; 100× Jg reduction at 0.4 nm) to previous best values in literature for MIMcaps with ALD dielectrics.
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2010.5703344