Ultra-low series resistance W/ErSi2/n+-Si and W/Pd2Si/p+-Si S/D electrodes for advanced CMOS platform

A formation technology of ultra-low series resistance CMOS source/drain (S/D) electrodes is developed. The silicide/silicon contact resistivity (R c ) of 8.0×10 -10 Ω·cm 2 and the electrode's sheet resistance (R sheet ) of less than 5.0 Ω/□ are achieved for both n- and pMOS using W/ErSi 2 and W...

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Bibliographic Details
Main Authors: Kuroda, R, Tanaka, H, Nakao, Y, Teramoto, A, Miyamoto, N, Sugawa, S, Ohmi, T
Format: Conference Proceeding
Language:English
Subjects:
CMOS integrated circuits
Electrodes
Metals
MOS devices
Silicidation
Silicides
Silicon
Online Access:Request full text
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Description
Summary:A formation technology of ultra-low series resistance CMOS source/drain (S/D) electrodes is developed. The silicide/silicon contact resistivity (R c ) of 8.0×10 -10 Ω·cm 2 and the electrode's sheet resistance (R sheet ) of less than 5.0 Ω/□ are achieved for both n- and pMOS using W/ErSi 2 and W/Pd 2 Si metal stacked silicide structures. For the first time, FD-SOI CMOS with the developed S/D electrodes was fabricated and the ring oscillator speed performance was evaluated.
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2010.5703425