RAAPS: Reliability Aware ArchC based Processor Simulator

In semiconductor industry, designing a SoC is a complex process. Designing reliable SoCs includes study of various configurations involving different operating conditions and considering both hard and soft errors. Designers at higher level of abstraction already have many ways to remove or handle so...

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Bibliographic Details
Main Authors: Gupta, T, Bertolini, C, Heron, O, Ventroux, N, Zimmer, T, Marc, F
Format: Conference Proceeding
Language:English
Subjects:
Benchmark testing
Failure analysis
Integrated circuit modeling
Integrated circuit reliability
Libraries
Power demand
Online Access:Request full text
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Summary:In semiconductor industry, designing a SoC is a complex process. Designing reliable SoCs includes study of various configurations involving different operating conditions and considering both hard and soft errors. Designers at higher level of abstraction already have many ways to remove or handle soft errors. This paper aims at analyzing hard errors at functional level. We propose a methodology using state of the art failure models and simulators to provide the cumulative failure rate for a processor simulated at functional level.
ISSN:1930-8841
2374-8036
DOI:10.1109/IIRW.2010.5706512