Loading…
Automated mapping of regular communication graphs on mesh interconnects
Network contention has a significantly adverse effect on the performance of parallel applications with increasing size of parallel machines. Machines of the petascale era are forcing application developers to map tasks intelligently to job partitions to achieve the best performance possible. This pa...
Saved in:
Main Authors: | , , , |
---|---|
Format: | Conference Proceeding |
Language: | English |
Subjects: | |
Online Access: | Request full text |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
cited_by | |
---|---|
cites | |
container_end_page | 10 |
container_issue | |
container_start_page | 1 |
container_title | |
container_volume | |
creator | Bhatelé, Abhinav Gupta, G R Kalé, Laxmikant V I-Hsin Chung |
description | Network contention has a significantly adverse effect on the performance of parallel applications with increasing size of parallel machines. Machines of the petascale era are forcing application developers to map tasks intelligently to job partitions to achieve the best performance possible. This paper presents a framework for automated mapping of parallel applications with regular communication graphs to two and three dimensional mesh and torus networks. This framework will save much effort on the part of application developers to generate mappings for their individual applications. One component of the framework is a process topology analyzer to find regular patterns and if found, to determine the dimensions of the communication graphs of applications. The other component is a suite of heuristic techniques for mapping 2D object grids to 2D and 3D processor meshes. The framework chooses the best heuristic from the suite for a given object grid and processor mesh pair based on the hop-bytes metric. We show performance improvements using the framework, for a 2D Stencil benchmark in MPI and the Weather Research and Forecasting model running on the IBM Blue Gene/P. We also compare our algorithms with others discussed in literature. |
doi_str_mv | 10.1109/HIPC.2010.5713190 |
format | conference_proceeding |
fullrecord | <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_5713190</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5713190</ieee_id><sourcerecordid>5713190</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-abfe67f0ec90c1e731b7568312ce2d5ec0d38fece7c89d62c2eb3112633d23563</originalsourceid><addsrcrecordid>eNotkMtqwzAURNUX1E39AaUb_YBTXV1LspYhNA8ItIvsgyxfOyrxAz8W_fsa6tnMDANnMYy9gVgDCPtxOH5v11LMVRlAsOKOvUAq0zRTUph7FkmdikQg6AcWW5MtG2TqkUUzIE2MVPqZxcPwI2YpaSxixPabaWxrN1LBa9d1oal4W_Kequnmeu7bup6a4N0Y2oZXveuuA59TTcOVh2ak3rdNQ34cXtlT6W4DxYuv2Hn3ed4ektPX_rjdnJJgxZi4vCRtSkHeCg9kEHKjdIYgPclCkRcFZiV5Mj6zhZZeUo4AUiMWEpXGFXv_xwYiunR9qF3_e1kuwT_FT1Fp</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Automated mapping of regular communication graphs on mesh interconnects</title><source>IEEE Xplore All Conference Series</source><creator>Bhatelé, Abhinav ; Gupta, G R ; Kalé, Laxmikant V ; I-Hsin Chung</creator><creatorcontrib>Bhatelé, Abhinav ; Gupta, G R ; Kalé, Laxmikant V ; I-Hsin Chung</creatorcontrib><description>Network contention has a significantly adverse effect on the performance of parallel applications with increasing size of parallel machines. Machines of the petascale era are forcing application developers to map tasks intelligently to job partitions to achieve the best performance possible. This paper presents a framework for automated mapping of parallel applications with regular communication graphs to two and three dimensional mesh and torus networks. This framework will save much effort on the part of application developers to generate mappings for their individual applications. One component of the framework is a process topology analyzer to find regular patterns and if found, to determine the dimensions of the communication graphs of applications. The other component is a suite of heuristic techniques for mapping 2D object grids to 2D and 3D processor meshes. The framework chooses the best heuristic from the suite for a given object grid and processor mesh pair based on the hop-bytes metric. We show performance improvements using the framework, for a 2D Stencil benchmark in MPI and the Weather Research and Forecasting model running on the IBM Blue Gene/P. We also compare our algorithms with others discussed in literature.</description><identifier>ISSN: 1094-7256</identifier><identifier>ISBN: 9781424485185</identifier><identifier>ISBN: 1424485185</identifier><identifier>EISSN: 2640-0316</identifier><identifier>EISBN: 1424485207</identifier><identifier>EISBN: 1424485193</identifier><identifier>EISBN: 9781424485192</identifier><identifier>EISBN: 9781424485208</identifier><identifier>DOI: 10.1109/HIPC.2010.5713190</identifier><language>eng</language><publisher>IEEE</publisher><subject>Bandwidth ; Heuristic algorithms ; Measurement ; Meteorology ; Network topology ; Three dimensional displays ; Topology</subject><ispartof>2010 International Conference on High Performance Computing, 2010, p.1-10</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5713190$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,27904,54533,54898,54910</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5713190$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Bhatelé, Abhinav</creatorcontrib><creatorcontrib>Gupta, G R</creatorcontrib><creatorcontrib>Kalé, Laxmikant V</creatorcontrib><creatorcontrib>I-Hsin Chung</creatorcontrib><title>Automated mapping of regular communication graphs on mesh interconnects</title><title>2010 International Conference on High Performance Computing</title><addtitle>HIPC</addtitle><description>Network contention has a significantly adverse effect on the performance of parallel applications with increasing size of parallel machines. Machines of the petascale era are forcing application developers to map tasks intelligently to job partitions to achieve the best performance possible. This paper presents a framework for automated mapping of parallel applications with regular communication graphs to two and three dimensional mesh and torus networks. This framework will save much effort on the part of application developers to generate mappings for their individual applications. One component of the framework is a process topology analyzer to find regular patterns and if found, to determine the dimensions of the communication graphs of applications. The other component is a suite of heuristic techniques for mapping 2D object grids to 2D and 3D processor meshes. The framework chooses the best heuristic from the suite for a given object grid and processor mesh pair based on the hop-bytes metric. We show performance improvements using the framework, for a 2D Stencil benchmark in MPI and the Weather Research and Forecasting model running on the IBM Blue Gene/P. We also compare our algorithms with others discussed in literature.</description><subject>Bandwidth</subject><subject>Heuristic algorithms</subject><subject>Measurement</subject><subject>Meteorology</subject><subject>Network topology</subject><subject>Three dimensional displays</subject><subject>Topology</subject><issn>1094-7256</issn><issn>2640-0316</issn><isbn>9781424485185</isbn><isbn>1424485185</isbn><isbn>1424485207</isbn><isbn>1424485193</isbn><isbn>9781424485192</isbn><isbn>9781424485208</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotkMtqwzAURNUX1E39AaUb_YBTXV1LspYhNA8ItIvsgyxfOyrxAz8W_fsa6tnMDANnMYy9gVgDCPtxOH5v11LMVRlAsOKOvUAq0zRTUph7FkmdikQg6AcWW5MtG2TqkUUzIE2MVPqZxcPwI2YpaSxixPabaWxrN1LBa9d1oal4W_Kequnmeu7bup6a4N0Y2oZXveuuA59TTcOVh2ak3rdNQ34cXtlT6W4DxYuv2Hn3ed4ektPX_rjdnJJgxZi4vCRtSkHeCg9kEHKjdIYgPclCkRcFZiV5Mj6zhZZeUo4AUiMWEpXGFXv_xwYiunR9qF3_e1kuwT_FT1Fp</recordid><startdate>201012</startdate><enddate>201012</enddate><creator>Bhatelé, Abhinav</creator><creator>Gupta, G R</creator><creator>Kalé, Laxmikant V</creator><creator>I-Hsin Chung</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201012</creationdate><title>Automated mapping of regular communication graphs on mesh interconnects</title><author>Bhatelé, Abhinav ; Gupta, G R ; Kalé, Laxmikant V ; I-Hsin Chung</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-abfe67f0ec90c1e731b7568312ce2d5ec0d38fece7c89d62c2eb3112633d23563</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Bandwidth</topic><topic>Heuristic algorithms</topic><topic>Measurement</topic><topic>Meteorology</topic><topic>Network topology</topic><topic>Three dimensional displays</topic><topic>Topology</topic><toplevel>online_resources</toplevel><creatorcontrib>Bhatelé, Abhinav</creatorcontrib><creatorcontrib>Gupta, G R</creatorcontrib><creatorcontrib>Kalé, Laxmikant V</creatorcontrib><creatorcontrib>I-Hsin Chung</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bhatelé, Abhinav</au><au>Gupta, G R</au><au>Kalé, Laxmikant V</au><au>I-Hsin Chung</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Automated mapping of regular communication graphs on mesh interconnects</atitle><btitle>2010 International Conference on High Performance Computing</btitle><stitle>HIPC</stitle><date>2010-12</date><risdate>2010</risdate><spage>1</spage><epage>10</epage><pages>1-10</pages><issn>1094-7256</issn><eissn>2640-0316</eissn><isbn>9781424485185</isbn><isbn>1424485185</isbn><eisbn>1424485207</eisbn><eisbn>1424485193</eisbn><eisbn>9781424485192</eisbn><eisbn>9781424485208</eisbn><abstract>Network contention has a significantly adverse effect on the performance of parallel applications with increasing size of parallel machines. Machines of the petascale era are forcing application developers to map tasks intelligently to job partitions to achieve the best performance possible. This paper presents a framework for automated mapping of parallel applications with regular communication graphs to two and three dimensional mesh and torus networks. This framework will save much effort on the part of application developers to generate mappings for their individual applications. One component of the framework is a process topology analyzer to find regular patterns and if found, to determine the dimensions of the communication graphs of applications. The other component is a suite of heuristic techniques for mapping 2D object grids to 2D and 3D processor meshes. The framework chooses the best heuristic from the suite for a given object grid and processor mesh pair based on the hop-bytes metric. We show performance improvements using the framework, for a 2D Stencil benchmark in MPI and the Weather Research and Forecasting model running on the IBM Blue Gene/P. We also compare our algorithms with others discussed in literature.</abstract><pub>IEEE</pub><doi>10.1109/HIPC.2010.5713190</doi><tpages>10</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 1094-7256 |
ispartof | 2010 International Conference on High Performance Computing, 2010, p.1-10 |
issn | 1094-7256 2640-0316 |
language | eng |
recordid | cdi_ieee_primary_5713190 |
source | IEEE Xplore All Conference Series |
subjects | Bandwidth Heuristic algorithms Measurement Meteorology Network topology Three dimensional displays Topology |
title | Automated mapping of regular communication graphs on mesh interconnects |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-25T20%3A28%3A33IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Automated%20mapping%20of%20regular%20communication%20graphs%20on%20mesh%20interconnects&rft.btitle=2010%20International%20Conference%20on%20High%20Performance%20Computing&rft.au=Bhatele%CC%81,%20Abhinav&rft.date=2010-12&rft.spage=1&rft.epage=10&rft.pages=1-10&rft.issn=1094-7256&rft.eissn=2640-0316&rft.isbn=9781424485185&rft.isbn_list=1424485185&rft_id=info:doi/10.1109/HIPC.2010.5713190&rft.eisbn=1424485207&rft.eisbn_list=1424485193&rft.eisbn_list=9781424485192&rft.eisbn_list=9781424485208&rft_dat=%3Cieee_CHZPO%3E5713190%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i90t-abfe67f0ec90c1e731b7568312ce2d5ec0d38fece7c89d62c2eb3112633d23563%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5713190&rfr_iscdi=true |