An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS

New characterizing system for within-die delay variations of individual standard cells is presented. The proposed characterizing system is able to measure rising and falling delay variations separately by directly measuring the input and output waveforms of individual gate using an on-chip sampling...

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Bibliographic Details
Main Authors: Xin Zhang, Ishida, K, Takamiya, M, Sakurai, T
Format: Conference Proceeding
Language:English
Subjects:
Delay
Generators
Layout
Logic gates
Oscilloscopes
System-on-a-chip
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Description
Summary:New characterizing system for within-die delay variations of individual standard cells is presented. The proposed characterizing system is able to measure rising and falling delay variations separately by directly measuring the input and output waveforms of individual gate using an on-chip sampling oscilloscope in 65nm CMOS process. 7 types of standard cells are measured with 60 DUT's for each type. Thanks to the proposed system, a relationship between the rising and falling delay variations and the active area of the standard cells is experimentally shown for the first time.
ISSN:2153-6961
2153-697X
DOI:10.1109/ASPDAC.2011.5722162