An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS

New characterizing system for within-die delay variations of individual standard cells is presented. The proposed characterizing system is able to measure rising and falling delay variations separately by directly measuring the input and output waveforms of individual gate using an on-chip sampling...

Full description

Saved in:
Bibliographic Details
Main Authors: Xin Zhang, Ishida, K, Takamiya, M, Sakurai, T
Format: Conference Proceeding
Language:English
Subjects:
Delay
Generators
Layout
Logic gates
Oscilloscopes
System-on-a-chip
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by
cites
container_end_page 110
container_issue
container_start_page 109
container_title
container_volume
creator Xin Zhang
Ishida, K
Takamiya, M
Sakurai, T
description New characterizing system for within-die delay variations of individual standard cells is presented. The proposed characterizing system is able to measure rising and falling delay variations separately by directly measuring the input and output waveforms of individual gate using an on-chip sampling oscilloscope in 65nm CMOS process. 7 types of standard cells are measured with 60 DUT's for each type. Thanks to the proposed system, a relationship between the rising and falling delay variations and the active area of the standard cells is experimentally shown for the first time.
doi_str_mv 10.1109/ASPDAC.2011.5722162
format conference_proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5722162</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5722162</ieee_id><sourcerecordid>5722162</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-8e63f04568b2ae1e7f4e876dc3eee51b43d3e3382c03e88fae7089046dba01573</originalsourceid><addsrcrecordid>eNo9kMtuwjAURN2XVEr5Ajb-gVC_7Syj9ClRUQkW3SET3xRXiYPskIp-fZFKO5tZHJ1ZDEJTSmaUkvyuWL7dF-WMEUpnUjNGFTtDN1QwIbSkQp-jEaOSZyrX7xdokmvzx6S8_GeKXqNJSp_kGMk0z-kIDUXAXciqrd_hamujrXqI_tuHD5wOqYcW113EX77f-pA5D9hBYw94sNHb3ncBt2DTPkILocddjX1wfvBubxucehucjQ5X0DTpSLCSWWhx-bpY3qKr2jYJJqceo9Xjw6p8zuaLp5eymGc-J31mQPGaCKnMhlmgoGsBRitXcQCQdCO448C5YRXhYExtQROTE6HcxhIqNR-j6e-sPwrrXfStjYf16UH-A7UpYe0</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Xin Zhang ; Ishida, K ; Takamiya, M ; Sakurai, T</creator><creatorcontrib>Xin Zhang ; Ishida, K ; Takamiya, M ; Sakurai, T</creatorcontrib><description>New characterizing system for within-die delay variations of individual standard cells is presented. The proposed characterizing system is able to measure rising and falling delay variations separately by directly measuring the input and output waveforms of individual gate using an on-chip sampling oscilloscope in 65nm CMOS process. 7 types of standard cells are measured with 60 DUT's for each type. Thanks to the proposed system, a relationship between the rising and falling delay variations and the active area of the standard cells is experimentally shown for the first time.</description><identifier>ISSN: 2153-6961</identifier><identifier>ISBN: 9781424475155</identifier><identifier>ISBN: 1424475155</identifier><identifier>EISSN: 2153-697X</identifier><identifier>EISBN: 1424475147</identifier><identifier>EISBN: 1424475163</identifier><identifier>EISBN: 9781424475162</identifier><identifier>EISBN: 9781424475148</identifier><identifier>DOI: 10.1109/ASPDAC.2011.5722162</identifier><language>eng</language><publisher>IEEE</publisher><subject>Delay ; Generators ; Layout ; Logic gates ; Oscilloscopes ; System-on-a-chip</subject><ispartof>16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 2011, p.109-110</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5722162$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54530,54895,54907</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5722162$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Xin Zhang</creatorcontrib><creatorcontrib>Ishida, K</creatorcontrib><creatorcontrib>Takamiya, M</creatorcontrib><creatorcontrib>Sakurai, T</creatorcontrib><title>An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS</title><title>16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)</title><addtitle>ASPDAC</addtitle><description>New characterizing system for within-die delay variations of individual standard cells is presented. The proposed characterizing system is able to measure rising and falling delay variations separately by directly measuring the input and output waveforms of individual gate using an on-chip sampling oscilloscope in 65nm CMOS process. 7 types of standard cells are measured with 60 DUT's for each type. Thanks to the proposed system, a relationship between the rising and falling delay variations and the active area of the standard cells is experimentally shown for the first time.</description><subject>Delay</subject><subject>Generators</subject><subject>Layout</subject><subject>Logic gates</subject><subject>Oscilloscopes</subject><subject>System-on-a-chip</subject><issn>2153-6961</issn><issn>2153-697X</issn><isbn>9781424475155</isbn><isbn>1424475155</isbn><isbn>1424475147</isbn><isbn>1424475163</isbn><isbn>9781424475162</isbn><isbn>9781424475148</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo9kMtuwjAURN2XVEr5Ajb-gVC_7Syj9ClRUQkW3SET3xRXiYPskIp-fZFKO5tZHJ1ZDEJTSmaUkvyuWL7dF-WMEUpnUjNGFTtDN1QwIbSkQp-jEaOSZyrX7xdokmvzx6S8_GeKXqNJSp_kGMk0z-kIDUXAXciqrd_hamujrXqI_tuHD5wOqYcW113EX77f-pA5D9hBYw94sNHb3ncBt2DTPkILocddjX1wfvBubxucehucjQ5X0DTpSLCSWWhx-bpY3qKr2jYJJqceo9Xjw6p8zuaLp5eymGc-J31mQPGaCKnMhlmgoGsBRitXcQCQdCO448C5YRXhYExtQROTE6HcxhIqNR-j6e-sPwrrXfStjYf16UH-A7UpYe0</recordid><startdate>201101</startdate><enddate>201101</enddate><creator>Xin Zhang</creator><creator>Ishida, K</creator><creator>Takamiya, M</creator><creator>Sakurai, T</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201101</creationdate><title>An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS</title><author>Xin Zhang ; Ishida, K ; Takamiya, M ; Sakurai, T</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-8e63f04568b2ae1e7f4e876dc3eee51b43d3e3382c03e88fae7089046dba01573</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Delay</topic><topic>Generators</topic><topic>Layout</topic><topic>Logic gates</topic><topic>Oscilloscopes</topic><topic>System-on-a-chip</topic><toplevel>online_resources</toplevel><creatorcontrib>Xin Zhang</creatorcontrib><creatorcontrib>Ishida, K</creatorcontrib><creatorcontrib>Takamiya, M</creatorcontrib><creatorcontrib>Sakurai, T</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Xin Zhang</au><au>Ishida, K</au><au>Takamiya, M</au><au>Sakurai, T</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS</atitle><btitle>16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)</btitle><stitle>ASPDAC</stitle><date>2011-01</date><risdate>2011</risdate><spage>109</spage><epage>110</epage><pages>109-110</pages><issn>2153-6961</issn><eissn>2153-697X</eissn><isbn>9781424475155</isbn><isbn>1424475155</isbn><eisbn>1424475147</eisbn><eisbn>1424475163</eisbn><eisbn>9781424475162</eisbn><eisbn>9781424475148</eisbn><abstract>New characterizing system for within-die delay variations of individual standard cells is presented. The proposed characterizing system is able to measure rising and falling delay variations separately by directly measuring the input and output waveforms of individual gate using an on-chip sampling oscilloscope in 65nm CMOS process. 7 types of standard cells are measured with 60 DUT's for each type. Thanks to the proposed system, a relationship between the rising and falling delay variations and the active area of the standard cells is experimentally shown for the first time.</abstract><pub>IEEE</pub><doi>10.1109/ASPDAC.2011.5722162</doi><tpages>2</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 2153-6961
ispartof 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 2011, p.109-110
issn 2153-6961
2153-697X
language eng
recordid cdi_ieee_primary_5722162
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Delay
Generators
Layout
Logic gates
Oscilloscopes
System-on-a-chip
title An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-29T02%3A46%3A01IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=An%20on-chip%20characterizing%20system%20for%20within-die%20delay%20variation%20measurement%20of%20individual%20standard%20cells%20in%2065-nm%20CMOS&rft.btitle=16th%20Asia%20and%20South%20Pacific%20Design%20Automation%20Conference%20(ASP-DAC%202011)&rft.au=Xin%20Zhang&rft.date=2011-01&rft.spage=109&rft.epage=110&rft.pages=109-110&rft.issn=2153-6961&rft.eissn=2153-697X&rft.isbn=9781424475155&rft.isbn_list=1424475155&rft_id=info:doi/10.1109/ASPDAC.2011.5722162&rft.eisbn=1424475147&rft.eisbn_list=1424475163&rft.eisbn_list=9781424475162&rft.eisbn_list=9781424475148&rft_dat=%3Cieee_6IE%3E5722162%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i90t-8e63f04568b2ae1e7f4e876dc3eee51b43d3e3382c03e88fae7089046dba01573%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5722162&rfr_iscdi=true