A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme

The authors present a 40-MFLOPS 32-bit floating-point processor (FP) which is a component chip for a data-driven single-board processor. The FP is the first practical LSI chip which has introduced the elastic pipeline scheme. All parts in the FP are autonomously controlled by self-timed circuits, an...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1989-10, Vol.24 (5), p.1341-1347
Main Authors: Komori, S., Takata, H., Tamura, T., Asai, F., Ohno, T., Tomisawa, O., Yamasaki, T., Shima, K., Nishikawa, H., Terada, H.
Format: Article
Language:English
Subjects:
990200 - Mathematics & Computers
Applied sciences
ARRAY PROCESSORS
Automatic control
Circuit properties
Circuits
DESIGN
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
Job shop scheduling
Laboratories
Large scale integration
Large-scale systems
MEMORY DEVICES
Multiprocessing systems
PARALLEL PROCESSING
Pipeline processing
Processor scheduling
PROGRAMMING
Throughput
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Summary:The authors present a 40-MFLOPS 32-bit floating-point processor (FP) which is a component chip for a data-driven single-board processor. The FP is the first practical LSI chip which has introduced the elastic pipeline scheme. All parts in the FP are autonomously controlled by self-timed circuits, and no system clock is needed for processing. The elastic pipeline scheme provides data buffering capability and stabilization of circuit operation at the same time. Pipelining has been extensively utilized so that high throughput over 40-MFLOPS can be achieved. An automatic power conservation technique, called 'latch mode control', is also described.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.1989.572611