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A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme

The authors present a 40-MFLOPS 32-bit floating-point processor (FP) which is a component chip for a data-driven single-board processor. The FP is the first practical LSI chip which has introduced the elastic pipeline scheme. All parts in the FP are autonomously controlled by self-timed circuits, an...

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Published in:	IEEE journal of solid-state circuits 1989-10, Vol.24 (5), p.1341-1347
Main Authors:	Komori, S., Takata, H., Tamura, T., Asai, F., Ohno, T., Tomisawa, O., Yamasaki, T., Shima, K., Nishikawa, H., Terada, H.
Format:	Article
Language:	English
Subjects:	990200 - Mathematics & Computers Applied sciences ARRAY PROCESSORS Automatic control Circuit properties Circuits DESIGN Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE Job shop scheduling Laboratories Large scale integration Large-scale systems MEMORY DEVICES Multiprocessing systems PARALLEL PROCESSING Pipeline processing Processor scheduling PROGRAMMING Throughput
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cited_by	cdi_FETCH-LOGICAL-c347t-87092addeaaf25ed50fe3395aab131c4dbd30d5bd36937c44aadac4d9f23f30f3
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container_end_page	1347
container_issue	5
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container_title	IEEE journal of solid-state circuits
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creator	Komori, S. Takata, H. Tamura, T. Asai, F. Ohno, T. Tomisawa, O. Yamasaki, T. Shima, K. Nishikawa, H. Terada, H.
description	The authors present a 40-MFLOPS 32-bit floating-point processor (FP) which is a component chip for a data-driven single-board processor. The FP is the first practical LSI chip which has introduced the elastic pipeline scheme. All parts in the FP are autonomously controlled by self-timed circuits, and no system clock is needed for processing. The elastic pipeline scheme provides data buffering capability and stabilization of circuit operation at the same time. Pipelining has been extensively utilized so that high throughput over 40-MFLOPS can be achieved. An automatic power conservation technique, called 'latch mode control', is also described.< >
doi_str_mv	10.1109/JSSC.1989.572611
format	article
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The FP is the first practical LSI chip which has introduced the elastic pipeline scheme. All parts in the FP are autonomously controlled by self-timed circuits, and no system clock is needed for processing. The elastic pipeline scheme provides data buffering capability and stabilization of circuit operation at the same time. Pipelining has been extensively utilized so that high throughput over 40-MFLOPS can be achieved. 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Takata, H. ; Tamura, T. ; Asai, F. ; Ohno, T. ; Tomisawa, O. ; Yamasaki, T. ; Shima, K. ; Nishikawa, H. ; Terada, H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c347t-87092addeaaf25ed50fe3395aab131c4dbd30d5bd36937c44aadac4d9f23f30f3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1989</creationdate><topic>990200 - Mathematics & Computers</topic><topic>Applied sciences</topic><topic>ARRAY PROCESSORS</topic><topic>Automatic control</topic><topic>Circuit properties</topic><topic>Circuits</topic><topic>DESIGN</topic><topic>Digital circuits</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE</topic><topic>Job shop scheduling</topic><topic>Laboratories</topic><topic>Large scale integration</topic><topic>Large-scale systems</topic><topic>MEMORY DEVICES</topic><topic>Multiprocessing systems</topic><topic>PARALLEL PROCESSING</topic><topic>Pipeline processing</topic><topic>Processor scheduling</topic><topic>PROGRAMMING</topic><topic>Throughput</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Komori, S.</creatorcontrib><creatorcontrib>Takata, H.</creatorcontrib><creatorcontrib>Tamura, T.</creatorcontrib><creatorcontrib>Asai, F.</creatorcontrib><creatorcontrib>Ohno, T.</creatorcontrib><creatorcontrib>Tomisawa, O.</creatorcontrib><creatorcontrib>Yamasaki, T.</creatorcontrib><creatorcontrib>Shima, K.</creatorcontrib><creatorcontrib>Nishikawa, H.</creatorcontrib><creatorcontrib>Terada, H.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>OSTI.GOV</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Komori, S.</au><au>Takata, H.</au><au>Tamura, T.</au><au>Asai, F.</au><au>Ohno, T.</au><au>Tomisawa, O.</au><au>Yamasaki, T.</au><au>Shima, K.</au><au>Nishikawa, H.</au><au>Terada, H.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1989-10-01</date><risdate>1989</risdate><volume>24</volume><issue>5</issue><spage>1341</spage><epage>1347</epage><pages>1341-1347</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>The authors present a 40-MFLOPS 32-bit floating-point processor (FP) which is a component chip for a data-driven single-board processor. The FP is the first practical LSI chip which has introduced the elastic pipeline scheme. All parts in the FP are autonomously controlled by self-timed circuits, and no system clock is needed for processing. The elastic pipeline scheme provides data buffering capability and stabilization of circuit operation at the same time. Pipelining has been extensively utilized so that high throughput over 40-MFLOPS can be achieved. An automatic power conservation technique, called 'latch mode control', is also described.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/JSSC.1989.572611</doi><tpages>7</tpages></addata></record>
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source	IEEE Electronic Library (IEL) Journals
subjects	990200 - Mathematics & Computers Applied sciences ARRAY PROCESSORS Automatic control Circuit properties Circuits DESIGN Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE Job shop scheduling Laboratories Large scale integration Large-scale systems MEMORY DEVICES Multiprocessing systems PARALLEL PROCESSING Pipeline processing Processor scheduling PROGRAMMING Throughput
title	A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme
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