Multi-GHz systems clocking

• Main Author: Oklobdzija, V.G.
• Format: Conference Proceeding
• Language: English
• ISSN: 1523-553X
• DOI: 10.1109/ICASIC.2003.1277307

The microprocessor clock speed has been rising rapidly. As the clock speed increases, the number of logic levels in the critical path diminishes. In today's high speed processors, instructions are executed in one cycle, which is driven by a single-phase clock. Today 10 or less level of logic in the critical path is not uncommon. Never the less, the amount of logic between the two stages is decreasing further. Thus any overhead associated with the clock system and clocking mechanism that is directly and adversely affecting the machine performance is critically important. Clocking for high performance and low-power systems represent is a challenge given the rapid increase in clock frequency which has already reached multiple GHz rates. Expect that current clocking is to hold up to 10 GHz afterwards the pipeline boundaries starts to vanish while more exotic clocking techniques finds their use. Synchronous design is possible only in limited domains on the chip. A mix of synchronous and asynchronous design may emerge even in digital logic. This may represent the next design challenge in complex chip design.